ext (#3)

burrbull · web-flow · commit 558357b047db · 2025-06-21T10:51:43.000+02:00
diff --git a/.zed/settings.json b/.zed/settings.json
@@ -0,0 +1,15 @@
+{
+  "lsp": {
+    "rust-analyzer": {
+      "initialization_options": {
+        "cargo": {
+          "features": ["stm32g474"]
+        },
+        "check": {
+          "allTargets": false,
+          "targets": "thumbv7em-none-eabihf"
+        }
+      }
+    }
+  }
+}
diff --git a/Cargo.toml b/Cargo.toml
@@ -4,8 +4,8 @@ version = "0.1.0"
 edition = "2021"
 
 [dependencies]
-stm32f3 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies", optional = true }
-stm32h7 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies", features = ["critical-section"], optional = true }
+stm32f3 = { version = "0.16.0", optional = true }
+stm32h7 = { version = "0.16.0", optional = true }
 stm32g4 = { version = "0.16.0", optional = true }
 
 defmt = { version = "1", optional = true }
diff --git a/examples/stm32g4/src/bin/adc-trigger.rs b/examples/stm32g4/src/bin/adc-trigger.rs
@@ -16,9 +16,9 @@ use stm32g4xx_hal::{
     dma::{self, TransferExt, channel::DMAExt, config::DmaConfig},
     gpio::GpioExt,
     hrtim::{HrControltExt, HrPwmBuilderExt},
+    pac::{CorePeripherals, Peripherals},
     pwr::PwrExt,
     rcc::{self, RccExt},
-    stm32::{CorePeripherals, Peripherals},
 };
 
 #[entry]
diff --git a/examples/stm32g4/src/bin/capture-dma.rs b/examples/stm32g4/src/bin/capture-dma.rs
@@ -17,9 +17,9 @@ use stm32g4xx_hal::{
     dma::{TransferExt, channel::DMAExt, config::DmaConfig},
     gpio::GpioExt,
     hrtim::{HrControltExt, HrPwmBuilderExt, external_event::EevInputExt},
+    pac::Peripherals,
     pwr::PwrExt,
     rcc::{self, RccExt},
-    stm32::Peripherals,
 };
 
 #[entry]
diff --git a/examples/stm32g4/src/bin/capture.rs b/examples/stm32g4/src/bin/capture.rs
@@ -17,9 +17,9 @@ use stm32_hrtim::{
 use stm32g4xx_hal::{
     gpio::GpioExt,
     hrtim::{HrControltExt, HrPwmBuilderExt, external_event::EevInputExt},
+    pac::Peripherals,
     pwr::PwrExt,
     rcc::{self, RccExt},
-    stm32::Peripherals,
 };
 
 #[entry]
diff --git a/examples/stm32g4/src/bin/eev-comp.rs b/examples/stm32g4/src/bin/eev-comp.rs
@@ -21,10 +21,10 @@ use stm32g4xx_hal::{
     delay::SYSTDelayExt,
     gpio::{GpioExt, SignalEdge},
     hrtim::{HrControltExt, HrPwmBuilderExt, external_event::EevInputExt},
+    pac::{CorePeripherals, Peripherals},
     pwr::PwrExt,
     rcc::{self, RccExt},
     stasis::Freeze,
-    stm32::{CorePeripherals, Peripherals},
 };
 
 #[entry]
diff --git a/examples/stm32g4/src/bin/eev.rs b/examples/stm32g4/src/bin/eev.rs
@@ -18,9 +18,9 @@ use stm32_hrtim::{
 use stm32g4xx_hal::{
     gpio::GpioExt,
     hrtim::{HrControltExt, HrPwmBuilderExt, external_event::EevInputExt},
+    pac::Peripherals,
     pwr::PwrExt,
     rcc::{self, RccExt},
-    stm32::Peripherals,
 };
 
 #[entry]
diff --git a/examples/stm32g4/src/bin/flt.rs b/examples/stm32g4/src/bin/flt.rs
@@ -18,9 +18,9 @@ use stm32g4xx_hal::{
     delay::{DelayExt, SYSTDelayExt},
     gpio::GpioExt,
     hrtim::{HrControltExt, HrPwmBuilderExt, fault::FaultInput},
+    pac::{CorePeripherals, Peripherals},
     pwr::PwrExt,
     rcc::{self, RccExt},
-    stm32::{CorePeripherals, Peripherals},
     time::ExtU32,
 };
 
diff --git a/examples/stm32g4/src/bin/hrtim.rs b/examples/stm32g4/src/bin/hrtim.rs
@@ -13,9 +13,9 @@ use stm32g4xx_hal::{
     delay::{DelayExt, SYSTDelayExt},
     gpio::GpioExt,
     hrtim::{HrControltExt, HrPwmBuilderExt},
+    pac::{CorePeripherals, Peripherals},
     pwr::PwrExt,
     rcc::{self, RccExt},
-    stm32::{CorePeripherals, Peripherals},
     time::ExtU32,
 };
 
diff --git a/examples/stm32g4/src/bin/master.rs b/examples/stm32g4/src/bin/master.rs
@@ -15,9 +15,9 @@ use stm32g4xx_hal::{
     delay::{DelayExt, SYSTDelayExt},
     gpio::GpioExt,
     hrtim::{HrControltExt, HrPwmBuilderExt},
+    pac::{CorePeripherals, Peripherals},
     pwr::PwrExt,
     rcc::{self, RccExt},
-    stm32::{CorePeripherals, Peripherals},
     time::ExtU32,
 };
 
diff --git a/src/capture.rs b/src/capture.rs
@@ -1,13 +1,8 @@
-use super::timer;
-
-#[cfg(feature = "hrtim_v2")]
-use crate::pac::HRTIM_TIMF;
-use crate::pac::{HRTIM_TIMA, HRTIM_TIMB, HRTIM_TIMC, HRTIM_TIMD, HRTIM_TIME};
+use super::timer::{self, InstanceX};
+pub use super::timer::{Ch1, Ch2, ChExt};
+use crate::ext::{CptcrW, MasterExt, TimExt};
 use core::marker::PhantomData;
 
-pub struct Ch1;
-pub struct Ch2;
-
 pub struct Dma;
 pub struct NoDma;
 
@@ -161,108 +156,84 @@ pub fn dma_value_to_signed(x: u32, #[allow(unused_variables)] period: u16) -> i3
     }
 }
 
-macro_rules! impl_capture {
-    ($($TIMX:ident),+) => {$(
-        impl_capture!($TIMX: Ch1, cpt1r, cpt1cr, cpt1, cpt1ie, cpt1de, cpt1c);
-        impl_capture!($TIMX: Ch2, cpt2r, cpt2cr, cpt2, cpt2ie, cpt2de, cpt2c);
-    )+};
-
-    ($TIMX:ident: $CH:ident, $cptXr:ident, $cptXcr:ident, $cptX:ident, $cptXie:ident, $cptXde:ident, $cptXc:ident) => {
-        impl<PSCL> HrCapt<$TIMX, PSCL, $CH, NoDma> {
-            /// Add event to capture
-            ///
-            /// If multiple events are added, they will be ORed together meaning
-            /// that a capture will be trigger if any one of the events triggers
-            pub fn add_event<E: CaptureEvent<$TIMX, PSCL>>(&mut self, _event: &E) {
-                let tim = unsafe { &*$TIMX::ptr() };
-
-                // SAFETY: We are the only one with access to cptXYcr
-                unsafe {
-                    tim.$cptXcr().modify(|r, w| w.bits(r.bits() | E::BITS));
-                }
-            }
-
-            /// Remove event to capture
-            pub fn remove_event<E: CaptureEvent<$TIMX, PSCL>>(&mut self, _event: &E) {
-                let tim = unsafe { &*$TIMX::ptr() };
-
-                // SAFETY: We are the only one with access to cptXYcr
-                unsafe {
-                    tim.$cptXcr().modify(|r, w| w.bits(r.bits() & !E::BITS));
-                }
-            }
-
-            /// Force capture trigger now
-            pub fn trigger_now(&mut self) {
-                // SAFETY: We are the only one with access to cptXYcr
-                let tim = unsafe { &*$TIMX::ptr() };
-
-                tim.$cptXcr().modify(|_, w| w.swcpt().set_bit());
-            }
-
-            // TODO: It would be sufficient to instead of hr_control only require exclusive access to the owning timer
-            // however that would be hard to do since typically the capture device is a field of that same timer.
-            // Would it make more sense to have this method direcly on HrTim instead?
-            pub fn enable_interrupt(&mut self, enable: bool, _hr_control: &mut super::HrPwmControl) {
-                let tim = unsafe { &*$TIMX::ptr() };
-
-                tim.dier().modify(|_r, w| w.$cptXie().bit(enable));
-            }
-
-            pub fn enable_dma(self, _ch: timer::DmaChannel<$TIMX>) -> HrCapt<$TIMX, PSCL, $CH, Dma> {
-                // SAFETY: We own the only insance of this timers dma channel, no one else can do this
-                let tim = unsafe { &*$TIMX::ptr() };
-                tim.dier().modify(|_r, w| w.$cptXde().set_bit());
-                HrCapt {
-                    _x: PhantomData
-                }
-            }
+impl<TIM: InstanceX, CH: ChExt, PSCL> HrCapt<TIM, PSCL, CH, NoDma> {
+    /// Add event to capture
+    ///
+    /// If multiple events are added, they will be ORed together meaning
+    /// that a capture will be trigger if any one of the events triggers
+    pub fn add_event<E: CaptureEvent<TIM, PSCL>>(&mut self, _event: &E) {
+        let tim = unsafe { &*TIM::ptr() };
+
+        // SAFETY: We are the only one with access to cptXYcr
+        unsafe {
+            tim.cptcr(CH::CH).modify(|r, w| w.bits(r.bits() | E::BITS));
         }
+    }
 
-        impl<PSCL, DMA> HrCapture for HrCapt<$TIMX, PSCL, $CH, DMA> {
-            fn get_last(&self) -> (u16, CountingDirection) {
-                let tim = unsafe { &*$TIMX::ptr() };
-                let data = tim.$cptXr().read();
-
-                #[cfg(feature = "hrtim_v2")]
-                let dir = match data.dir().bit() {
-                    true => CountingDirection::Down,
-                    false => CountingDirection::Up,
-                };
-                #[cfg(any(feature = "hrtim_v1", feature = "hrtim_v1_1"))]
-                let dir = CountingDirection::Up;
+    /// Remove event to capture
+    pub fn remove_event<E: CaptureEvent<TIM, PSCL>>(&mut self, _event: &E) {
+        let tim = unsafe { &*TIM::ptr() };
 
-                let value = data.cpt().bits();
+        // SAFETY: We are the only one with access to cptXYcr
+        unsafe {
+            tim.cptcr(CH::CH).modify(|r, w| w.bits(r.bits() & !E::BITS));
+        }
+    }
 
-                (value, dir)
-            }
+    /// Force capture trigger now
+    pub fn trigger_now(&mut self) {
+        // SAFETY: We are the only one with access to cptXYcr
+        let tim = unsafe { &*TIM::ptr() };
 
-            fn clear_interrupt(&mut self) {
-                let tim = unsafe { &*$TIMX::ptr() };
+        tim.cptcr(CH::CH).modify(|_, w| w.set_swcpt());
+    }
 
-                // No need for exclusive access since this is a write only register
-                tim.icr().write(|w| w.$cptXc().clear());
-            }
+    // TODO: It would be sufficient to instead of hr_control only require exclusive access to the owning timer
+    // however that would be hard to do since typically the capture device is a field of that same timer.
+    // Would it make more sense to have this method direcly on HrTim instead?
+    pub fn enable_interrupt(&mut self, enable: bool, _hr_control: &mut super::HrPwmControl) {
+        let tim = unsafe { &*TIM::ptr() };
 
-            fn is_pending(&self) -> bool {
-                let tim = unsafe { &*$TIMX::ptr() };
+        tim.dier().modify(|_r, w| w.cptie(CH::CH as _).bit(enable));
+    }
 
-                // No need for exclusive access since this is a read only register
-                tim.isr().read().$cptX().bit()
-            }
-        }
-    };
+    pub fn enable_dma(self, _ch: timer::DmaChannel<TIM>) -> HrCapt<TIM, PSCL, CH, Dma> {
+        // SAFETY: We own the only insance of this timers dma channel, no one else can do this
+        let tim = unsafe { &*TIM::ptr() };
+        tim.dier().modify(|_r, w| w.cptde(CH::CH as _).set_bit());
+        HrCapt { _x: PhantomData }
+    }
 }
 
-impl_capture! {
-    HRTIM_TIMA,
-    HRTIM_TIMB,
-    HRTIM_TIMC,
-    HRTIM_TIMD,
-    HRTIM_TIME
-}
+impl<TIM: InstanceX, CH: ChExt, PSCL, DMA> HrCapture for HrCapt<TIM, PSCL, CH, DMA> {
+    fn get_last(&self) -> (u16, CountingDirection) {
+        let tim = unsafe { &*TIM::ptr() };
+        let data = tim.cptr(CH::CH).read();
+
+        #[cfg(feature = "hrtim_v2")]
+        let dir = match data.dir().bit() {
+            true => CountingDirection::Down,
+            false => CountingDirection::Up,
+        };
+        #[cfg(any(feature = "hrtim_v1", feature = "hrtim_v1_1"))]
+        let dir = CountingDirection::Up;
+
+        let value = data.cpt().bits();
+
+        (value, dir)
+    }
 
-#[cfg(feature = "hrtim_v2")]
-impl_capture! {
-    HRTIM_TIMF
+    fn clear_interrupt(&mut self) {
+        let tim = unsafe { &*TIM::ptr() };
+
+        // No need for exclusive access since this is a write only register
+        tim.icr().write(|w| w.cptc(CH::CH as _).clear());
+    }
+
+    fn is_pending(&self) -> bool {
+        let tim = unsafe { &*TIM::ptr() };
+
+        // No need for exclusive access since this is a read only register
+        tim.isr().read().cpt(CH::CH as _).bit()
+    }
 }
diff --git a/src/compare_register.rs b/src/compare_register.rs
diff --git a/src/ext.rs b/src/ext.rs
diff --git a/src/lib.rs b/src/lib.rs
diff --git a/src/output.rs b/src/output.rs
diff --git a/src/timer.rs b/src/timer.rs
