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This adds code from http://web.archive.org/web/20190317154112/http://mygizmos.org/ols/Logic-Sniffer-FPGA-Spec.pdf (GPL2 with the option
to relicense it to any later version of that license) with reformatting
and without typos to set up the LUT bits.
The trigger setup starts with a delay to collect the required number of
pre-trigger samples. Afterwards, the remaining samples are captured or
further trigger stages follow.
Each of these extra stages mirrors what the user has defined as trigger
pattern: Level and edge triggers are combined and the state machine only
advances to the next stage if all levels and at least one edge meets the
conditions. Contrary to level triggers, edge triggers are ORed together.
This is an undocumented property of the Demon Core.
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