Skip to content

Commit 1eadac4

Browse files
committed
ensure aligned pointer cast
1 parent 46e99db commit 1eadac4

File tree

1 file changed

+14
-7
lines changed

1 file changed

+14
-7
lines changed

embassy-stm32/src/i2s.rs

Lines changed: 14 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,6 @@
11
//! Inter-IC Sound (I2S)
2+
use core::sync::atomic::{fence, Ordering};
3+
24
use embassy_hal_internal::into_ref;
35

46
use crate::dma::{ringbuffer, word, Channel, NoDma, TransferOptions, WritableRingBuffer};
@@ -264,6 +266,7 @@ impl<'d, T: Instance, C: Channel, W: word::Word> I2S<'d, T, C, W> {
264266

265267
let opts = TransferOptions {
266268
half_transfer_ir: true,
269+
267270
//the new_write() and new_read() always use circular mode
268271
..Default::default()
269272
};
@@ -312,19 +315,17 @@ impl<'d, T: Instance, C: Channel, W: word::Word> I2S<'d, T, C, W> {
312315
// spi_cfg.frequency = freq;
313316
// let spi = Spi::new_internal(peri, NoDma, NoDma, spi_cfg);
314317

315-
316-
// TODO move i2s to the new mux infra.
317-
//#[cfg(all(rcc_f4, not(stm32f410)))]
318-
//let pclk = unsafe { get_freqs() }.plli2s1_q.unwrap();
319-
//#[cfg(stm32f410)]
320-
let pclk = T::frequency();
318+
// TODO move i2s to the new mux infra.
319+
//#[cfg(all(rcc_f4, not(stm32f410)))]
320+
//let pclk = unsafe { get_freqs() }.plli2s1_q.unwrap();
321+
//#[cfg(stm32f410)]
322+
// let pclk = T::frequency();
321323
// #[cfg(all(rcc_f4, not(stm32f410)))]
322324
// let pclk = unsafe { get_freqs() }.plli2s1_q.unwrap();
323325

324326
// #[cfg(stm32f410)]
325327
// let pclk = T::frequency();
326328

327-
328329
// let (odd, div) = compute_baud_rate(pclk, freq, config.master_clock, config.format);
329330

330331
// #[cfg(any(spi_v1, spi_f1))]
@@ -421,6 +422,12 @@ impl<'d, T: Instance, C: Channel, W: word::Word> I2S<'d, T, C, W> {
421422
});
422423

423424
self.ring_buffer.request_stop();
425+
while self.ring_buffer.is_running() {}
426+
427+
// "Subsequent reads and writes cannot be moved ahead of preceding reads."
428+
fence(Ordering::SeqCst);
429+
430+
// self.ring_buffer.clear();
424431

425432
T::REGS.cr1().modify(|w| {
426433
w.set_spe(false);

0 commit comments

Comments
 (0)