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Merge pull request embassy-rs#2565 from caleb-garrett/hmac
STM32 HMAC
2 parents ee4afa4 + f0045b9 commit 4c7ed5e

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5 files changed

+110
-17
lines changed

5 files changed

+110
-17
lines changed

embassy-stm32/src/hash/mod.rs

Lines changed: 61 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -100,8 +100,9 @@ pub enum DataType {
100100

101101
/// Stores the state of the HASH peripheral for suspending/resuming
102102
/// digest calculation.
103-
pub struct Context {
103+
pub struct Context<'c> {
104104
first_word_sent: bool,
105+
key_sent: bool,
105106
buffer: [u8; HASH_BUFFER_LEN],
106107
buflen: usize,
107108
algo: Algorithm,
@@ -110,8 +111,11 @@ pub struct Context {
110111
str: u32,
111112
cr: u32,
112113
csr: [u32; NUM_CONTEXT_REGS],
114+
key: HmacKey<'c>,
113115
}
114116

117+
type HmacKey<'k> = Option<&'k [u8]>;
118+
115119
/// HASH driver.
116120
pub struct Hash<'d, T: Instance, D = NoDma> {
117121
_peripheral: PeripheralRef<'d, T>,
@@ -140,10 +144,11 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
140144
}
141145

142146
/// Starts computation of a new hash and returns the saved peripheral state.
143-
pub fn start(&mut self, algorithm: Algorithm, format: DataType) -> Context {
147+
pub fn start<'c>(&mut self, algorithm: Algorithm, format: DataType, key: HmacKey<'c>) -> Context<'c> {
144148
// Define a context for this new computation.
145149
let mut ctx = Context {
146150
first_word_sent: false,
151+
key_sent: false,
147152
buffer: [0; HASH_BUFFER_LEN],
148153
buflen: 0,
149154
algo: algorithm,
@@ -152,6 +157,7 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
152157
str: 0,
153158
cr: 0,
154159
csr: [0; NUM_CONTEXT_REGS],
160+
key,
155161
};
156162

157163
// Set the data type in the peripheral.
@@ -181,6 +187,14 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
181187
#[cfg(any(hash_v3, hash_v4))]
182188
T::regs().cr().modify(|w| w.set_algo(ctx.algo as u8));
183189

190+
// Configure HMAC mode if a key is provided.
191+
if let Some(key) = ctx.key {
192+
T::regs().cr().modify(|w| w.set_mode(true));
193+
if key.len() > 64 {
194+
T::regs().cr().modify(|w| w.set_lkey(true));
195+
}
196+
}
197+
184198
T::regs().cr().modify(|w| w.set_init(true));
185199

186200
// Store and return the state of the peripheral.
@@ -191,18 +205,30 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
191205
/// Restores the peripheral state using the given context,
192206
/// then updates the state with the provided data.
193207
/// Peripheral state is saved upon return.
194-
pub fn update_blocking(&mut self, ctx: &mut Context, input: &[u8]) {
208+
pub fn update_blocking<'c>(&mut self, ctx: &mut Context<'c>, input: &[u8]) {
209+
// Restore the peripheral state.
210+
self.load_context(&ctx);
211+
212+
// Load the HMAC key if provided.
213+
if !ctx.key_sent {
214+
if let Some(key) = ctx.key {
215+
self.accumulate_blocking(key);
216+
T::regs().str().write(|w| w.set_dcal(true));
217+
// Block waiting for digest.
218+
while !T::regs().sr().read().dinis() {}
219+
}
220+
ctx.key_sent = true;
221+
}
222+
195223
let mut data_waiting = input.len() + ctx.buflen;
196224
if data_waiting < DIGEST_BLOCK_SIZE || (data_waiting < ctx.buffer.len() && !ctx.first_word_sent) {
197225
// There isn't enough data to digest a block, so append it to the buffer.
198226
ctx.buffer[ctx.buflen..ctx.buflen + input.len()].copy_from_slice(input);
199227
ctx.buflen += input.len();
228+
self.store_context(ctx);
200229
return;
201230
}
202231

203-
// Restore the peripheral state.
204-
self.load_context(&ctx);
205-
206232
let mut ilen_remaining = input.len();
207233
let mut input_start = 0;
208234

@@ -261,21 +287,30 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
261287
/// then updates the state with the provided data.
262288
/// Peripheral state is saved upon return.
263289
#[cfg(hash_v2)]
264-
pub async fn update(&mut self, ctx: &mut Context, input: &[u8])
290+
pub async fn update<'c>(&mut self, ctx: &mut Context<'c>, input: &[u8])
265291
where
266292
D: crate::hash::Dma<T>,
267293
{
294+
// Restore the peripheral state.
295+
self.load_context(&ctx);
296+
297+
// Load the HMAC key if provided.
298+
if !ctx.key_sent {
299+
if let Some(key) = ctx.key {
300+
self.accumulate(key).await;
301+
}
302+
ctx.key_sent = true;
303+
}
304+
268305
let data_waiting = input.len() + ctx.buflen;
269306
if data_waiting < DIGEST_BLOCK_SIZE {
270307
// There isn't enough data to digest a block, so append it to the buffer.
271308
ctx.buffer[ctx.buflen..ctx.buflen + input.len()].copy_from_slice(input);
272309
ctx.buflen += input.len();
310+
self.store_context(ctx);
273311
return;
274312
}
275313

276-
// Restore the peripheral state.
277-
self.load_context(&ctx);
278-
279314
// Enable multiple DMA transfers.
280315
T::regs().cr().modify(|w| w.set_mdmat(true));
281316

@@ -319,7 +354,7 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
319354
/// The digest buffer must be large enough to accomodate a digest for the selected algorithm.
320355
/// The largest returned digest size is 128 bytes for SHA-512.
321356
/// Panics if the supplied digest buffer is too short.
322-
pub fn finish_blocking(&mut self, mut ctx: Context, digest: &mut [u8]) -> usize {
357+
pub fn finish_blocking<'c>(&mut self, mut ctx: Context<'c>, digest: &mut [u8]) -> usize {
323358
// Restore the peripheral state.
324359
self.load_context(&ctx);
325360

@@ -330,7 +365,14 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
330365
//Start the digest calculation.
331366
T::regs().str().write(|w| w.set_dcal(true));
332367

333-
// Block waiting for digest.
368+
// Load the HMAC key if provided.
369+
if let Some(key) = ctx.key {
370+
while !T::regs().sr().read().dinis() {}
371+
self.accumulate_blocking(key);
372+
T::regs().str().write(|w| w.set_dcal(true));
373+
}
374+
375+
// Block until digest computation is complete.
334376
while !T::regs().sr().read().dcis() {}
335377

336378
// Return the digest.
@@ -370,7 +412,7 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
370412
/// The largest returned digest size is 128 bytes for SHA-512.
371413
/// Panics if the supplied digest buffer is too short.
372414
#[cfg(hash_v2)]
373-
pub async fn finish(&mut self, mut ctx: Context, digest: &mut [u8]) -> usize
415+
pub async fn finish<'c>(&mut self, mut ctx: Context<'c>, digest: &mut [u8]) -> usize
374416
where
375417
D: crate::hash::Dma<T>,
376418
{
@@ -384,6 +426,11 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
384426
self.accumulate(&ctx.buffer[0..ctx.buflen]).await;
385427
ctx.buflen = 0;
386428

429+
// Load the HMAC key if provided.
430+
if let Some(key) = ctx.key {
431+
self.accumulate(key).await;
432+
}
433+
387434
// Wait for completion.
388435
poll_fn(|cx| {
389436
// Check if already done.
@@ -484,7 +531,7 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
484531
}
485532

486533
/// Save the peripheral state to a context.
487-
fn store_context(&mut self, ctx: &mut Context) {
534+
fn store_context<'c>(&mut self, ctx: &mut Context<'c>) {
488535
// Block waiting for data in ready.
489536
while !T::regs().sr().read().dinis() {}
490537

examples/stm32f7/Cargo.toml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@ critical-section = "1.1"
2929
embedded-storage = "0.3.1"
3030
static_cell = "2"
3131
sha2 = { version = "0.10.8", default-features = false }
32+
hmac = "0.12.1"
3233

3334
[profile.release]
3435
debug = 2

examples/stm32f7/src/bin/hash.rs

Lines changed: 23 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,9 +6,12 @@ use embassy_executor::Spawner;
66
use embassy_stm32::hash::*;
77
use embassy_stm32::{bind_interrupts, hash, peripherals, Config};
88
use embassy_time::Instant;
9+
use hmac::{Hmac, Mac};
910
use sha2::{Digest, Sha256};
1011
use {defmt_rtt as _, panic_probe as _};
1112

13+
type HmacSha256 = Hmac<Sha256>;
14+
1215
bind_interrupts!(struct Irqs {
1316
HASH_RNG => hash::InterruptHandler<peripherals::HASH>;
1417
});
@@ -26,7 +29,7 @@ async fn main(_spawner: Spawner) -> ! {
2629
let hw_start_time = Instant::now();
2730

2831
// Compute a digest in hardware.
29-
let mut context = hw_hasher.start(Algorithm::SHA256, DataType::Width8);
32+
let mut context = hw_hasher.start(Algorithm::SHA256, DataType::Width8, None);
3033
hw_hasher.update(&mut context, test_1).await;
3134
hw_hasher.update(&mut context, test_2).await;
3235
let mut hw_digest: [u8; 32] = [0; 32];
@@ -52,5 +55,24 @@ async fn main(_spawner: Spawner) -> ! {
5255
info!("Software Execution Time: {:?}", sw_execution_time);
5356
assert_eq!(hw_digest, sw_digest[..]);
5457

58+
let hmac_key: [u8; 64] = [0x55; 64];
59+
60+
// Compute HMAC in hardware.
61+
let mut sha256hmac_context = hw_hasher.start(Algorithm::SHA256, DataType::Width8, Some(&hmac_key));
62+
hw_hasher.update(&mut sha256hmac_context, test_1).await;
63+
hw_hasher.update(&mut sha256hmac_context, test_2).await;
64+
let mut hw_hmac: [u8; 32] = [0; 32];
65+
hw_hasher.finish(sha256hmac_context, &mut hw_hmac).await;
66+
67+
// Compute HMAC in software.
68+
let mut sw_mac = HmacSha256::new_from_slice(&hmac_key).unwrap();
69+
sw_mac.update(test_1);
70+
sw_mac.update(test_2);
71+
let sw_hmac = sw_mac.finalize().into_bytes();
72+
73+
info!("Hardware HMAC: {:?}", hw_hmac);
74+
info!("Software HMAC: {:?}", sw_hmac[..]);
75+
assert_eq!(hw_hmac, sw_hmac[..]);
76+
5577
loop {}
5678
}

tests/stm32/Cargo.toml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,7 @@ portable-atomic = { version = "1.5", features = [] }
7676

7777
chrono = { version = "^0.4", default-features = false, optional = true}
7878
sha2 = { version = "0.10.8", default-features = false }
79+
hmac = "0.12.1"
7980

8081
# BEGIN TESTS
8182
# Generated by gen_test.py. DO NOT EDIT.

tests/stm32/src/bin/hash.rs

Lines changed: 24 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,9 +9,12 @@ use embassy_executor::Spawner;
99
use embassy_stm32::dma::NoDma;
1010
use embassy_stm32::hash::*;
1111
use embassy_stm32::{bind_interrupts, hash, peripherals};
12+
use hmac::{Hmac, Mac};
1213
use sha2::{Digest, Sha224, Sha256};
1314
use {defmt_rtt as _, panic_probe as _};
1415

16+
type HmacSha256 = Hmac<Sha256>;
17+
1518
#[cfg(any(feature = "stm32l4a6zg", feature = "stm32h755zi", feature = "stm32h753zi"))]
1619
bind_interrupts!(struct Irqs {
1720
HASH_RNG => hash::InterruptHandler<peripherals::HASH>;
@@ -38,11 +41,11 @@ async fn main(_spawner: Spawner) {
3841
let test_3: &[u8] = b"a.ewtkluGWEBR.KAJRBTA,RMNRBG,FDMGB.kger.tkasjrbt.akrjtba.krjtba.ktmyna,nmbvtyliasd;gdrtba,sfvs.kgjzshd.gkbsr.tksejb.SDkfBSE.gkfgb>ESkfbSE>gkJSBESE>kbSE>fk";
3942

4043
// Start an SHA-256 digest.
41-
let mut sha256context = hw_hasher.start(Algorithm::SHA256, DataType::Width8);
44+
let mut sha256context = hw_hasher.start(Algorithm::SHA256, DataType::Width8, None);
4245
hw_hasher.update_blocking(&mut sha256context, test_1);
4346

4447
// Interrupt the SHA-256 digest to compute an SHA-224 digest.
45-
let mut sha224context = hw_hasher.start(Algorithm::SHA224, DataType::Width8);
48+
let mut sha224context = hw_hasher.start(Algorithm::SHA224, DataType::Width8, None);
4649
hw_hasher.update_blocking(&mut sha224context, test_3);
4750
let mut sha224_digest_buffer: [u8; 28] = [0; 28];
4851
let _ = hw_hasher.finish_blocking(sha224context, &mut sha224_digest_buffer);
@@ -73,6 +76,25 @@ async fn main(_spawner: Spawner) {
7376
info!("Software SHA-256 Digest: {:?}", sw_sha224_digest[..]);
7477
defmt::assert!(sha224_digest_buffer == sw_sha224_digest[..]);
7578

79+
let hmac_key: [u8; 64] = [0x55; 64];
80+
81+
// Compute HMAC in hardware.
82+
let mut sha256hmac_context = hw_hasher.start(Algorithm::SHA256, DataType::Width8, Some(&hmac_key));
83+
hw_hasher.update_blocking(&mut sha256hmac_context, test_1);
84+
hw_hasher.update_blocking(&mut sha256hmac_context, test_2);
85+
let mut hw_hmac: [u8; 32] = [0; 32];
86+
hw_hasher.finish_blocking(sha256hmac_context, &mut hw_hmac);
87+
88+
// Compute HMAC in software.
89+
let mut sw_mac = HmacSha256::new_from_slice(&hmac_key).unwrap();
90+
sw_mac.update(test_1);
91+
sw_mac.update(test_2);
92+
let sw_hmac = sw_mac.finalize().into_bytes();
93+
94+
info!("Hardware HMAC: {:?}", hw_hmac);
95+
info!("Software HMAC: {:?}", sw_hmac[..]);
96+
defmt::assert!(hw_hmac == sw_hmac[..]);
97+
7698
info!("Test OK");
7799
cortex_m::asm::bkpt();
78100
}

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