Update README.md

Author: Vadim Dyachkov

README.md

@@ -1,7 +1,5 @@
 # Hardware Description Languages
 
-![СПбПУ](http://www.spbstu.ru/university/organizational-documents/corporate-identity/identity-files/logo_main_en.png)
-
 1. Timing Analyzer `lab_ta`
 2. Design Rules `lab_dr`
 3. Verilog Hardware Description Language `verilog`
@@ -12,4 +10,4 @@
 8. In-System Memory Content Editor `lab_ismce`
 9. ModelSim Simulations `modelsim`
 10. Qsys & NIOS II `nios`
-11. Data transmission device `transmitter`
+11. Data transmission device `transmitter`