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ChinYikMingChinYikMing
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Implement minimal SBI (sysprog21#439)
SBI acts as a communication layer between S-mode software and M-mode hardware. To boot the Linux kernel, some minimal SBI extensions (v0.3) have to be implemented, and they are: 1. Base extension (EID=0x10) 2. Timer extension (EID=0x54494D45) The SRST extension (EID=0x53525354) is optional, so only the shutdown reason has been implemented.
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4 files changed

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-27
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4 files changed

+172
-27
lines changed

‎src/riscv.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -469,6 +469,9 @@ void rv_reset(riscv_t *rv, riscv_word_t pc)
469469
rv->csr_cycle = 0;
470470
rv->csr_mstatus = 0;
471471
rv->csr_misa |= MISA_SUPER | MISA_USER | MISA_I;
472+
rv->csr_mvendorid = RV_MVENDORID;
473+
rv->csr_marchid = RV_MARCHID;
474+
rv->csr_mimpid = RV_MIMPID;
472475
#if RV32_HAS(EXT_A)
473476
rv->csr_misa |= MISA_A;
474477
#endif

‎src/riscv.h‎

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,51 @@ enum {
9696
#define MSTATUS_MPIE (1 << MSTATUS_MPIE_SHIFT)
9797
#define MSTATUS_MPP (3 << MSTATUS_MPP_SHIFT)
9898

99+
/*
100+
* SBI functions must return a pair of values:
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*
102+
* struct sbiret {
103+
* long error;
104+
* long value;
105+
* };
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*
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* The error and value field will be set to register a0 and a1 respectively
108+
* after the SBI function return. The error field indicate whether the
109+
* SBI call is success or not. SBI_SUCCESS indicates success and
110+
* SBI_ERR_NOT_SUPPORTED indicates not supported failure. The value field is
111+
* the information based on the extension ID(EID) and SBI function ID(FID).
112+
*
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* SBI reference: https://github.com/riscv-non-isa/riscv-sbi-doc
114+
*
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*/
116+
#define SBI_SUCCESS 0
117+
#define SBI_ERR_NOT_SUPPORTED -2
118+
119+
/*
120+
* All of the functions in the base extension must be supported by
121+
* all SBI implementations.
122+
*/
123+
#define SBI_EID_BASE 0x10
124+
#define SBI_BASE_GET_SBI_SPEC_VERSION 0
125+
#define SBI_BASE_GET_SBI_IMPL_ID 1
126+
#define SBI_BASE_GET_SBI_IMPL_VERSION 2
127+
#define SBI_BASE_PROBE_EXTENSION 3
128+
#define SBI_BASE_GET_MVENDORID 4
129+
#define SBI_BASE_GET_MARCHID 5
130+
#define SBI_BASE_GET_MIMPID 6
131+
132+
/* Make supervisor to schedule the clock for next timer event. */
133+
#define SBI_EID_TIMER 0x54494D45
134+
#define SBI_TIMER_SET_TIMER 0
135+
136+
/* Allows the supervisor to request system-level reboot or shutdown. */
137+
#define SBI_EID_RST 0x53525354
138+
#define SBI_RST_SYSTEM_RESET 0
139+
140+
#define RV_MVENDORID 0x12345678
141+
#define RV_MARCHID ((1ULL << 31) | 1)
142+
#define RV_MIMPID 1
143+
99144
#define BLOCK_MAP_CAPACITY_BITS 10
100145

101146
/* forward declaration for internal structure */
@@ -294,6 +339,9 @@ typedef struct {
294339

295340
/* the data segment break address */
296341
riscv_word_t break_addr;
342+
343+
/* SBI timer */
344+
uint64_t timer;
297345
} vm_attr_t;
298346

299347
#ifdef __cplusplus

‎src/riscv_private.h‎

Lines changed: 13 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -110,16 +110,19 @@ struct riscv_internal {
110110
#endif
111111

112112
/* csr registers */
113-
uint64_t csr_cycle; /* Machine cycle counter */
114-
uint32_t csr_time[2]; /* Performance conter */
115-
uint32_t csr_mstatus; /* Machine status regester */
116-
uint32_t csr_mtvec; /* Machine trap-handler base address */
117-
uint32_t csr_misa; /* ISA and extensions */
118-
uint32_t csr_mtval; /* Machine bad address or instruction */
119-
uint32_t csr_mcause; /* Machine trap cause */
120-
uint32_t csr_mscratch; /* Scartch register for machine trap handler */
121-
uint32_t csr_mepc; /* Machine exception program counter */
122-
uint32_t csr_mip; /* Machine interrupt pending */
113+
uint64_t csr_cycle; /* Machine cycle counter */
114+
uint32_t csr_time[2]; /* Performance counter */
115+
uint32_t csr_mstatus; /* Machine status register */
116+
uint32_t csr_mtvec; /* Machine trap-handler base address */
117+
uint32_t csr_misa; /* ISA and extensions */
118+
uint32_t csr_mtval; /* Machine bad address or instruction */
119+
uint32_t csr_mcause; /* Machine trap cause */
120+
uint32_t csr_mscratch; /* Scratch register for machine trap handler */
121+
uint32_t csr_mepc; /* Machine exception program counter */
122+
uint32_t csr_mip; /* Machine interrupt pending */
123+
uint32_t csr_mvendorid; /* vendor ID */
124+
uint32_t csr_marchid; /* Architecture ID */
125+
uint32_t csr_mimpid; /* Implementation ID */
123126
uint32_t csr_mbadaddr;
124127

125128
bool compressed; /**< current instruction is compressed or not */

‎src/syscall.c‎

Lines changed: 108 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -23,23 +23,26 @@
2323
* system call: name, number
2424
*/
2525
/* clang-format off */
26-
#define SUPPORTED_SYSCALLS \
27-
_(close, 57) \
28-
_(lseek, 62) \
29-
_(read, 63) \
30-
_(write, 64) \
31-
_(fstat, 80) \
32-
_(exit, 93) \
33-
_(gettimeofday, 169) \
34-
_(brk, 214) \
35-
_(clock_gettime, 403) \
36-
_(open, 1024) \
37-
IIF(RV32_HAS(SDL))( \
38-
_(draw_frame, 0xBEEF) \
39-
_(setup_queue, 0xC0DE) \
40-
_(submit_queue, 0xFEED) \
41-
_(setup_audio, 0xBABE) \
42-
_(control_audio, 0xD00D) \
26+
#define SUPPORTED_SYSCALLS \
27+
_(close, 57) \
28+
_(lseek, 62) \
29+
_(read, 63) \
30+
_(write, 64) \
31+
_(fstat, 80) \
32+
_(exit, 93) \
33+
_(gettimeofday, 169) \
34+
_(brk, 214) \
35+
_(clock_gettime, 403) \
36+
_(open, 1024) \
37+
_(sbi_base, 0x10) \
38+
_(sbi_timer, 0x54494D45) \
39+
_(sbi_rst, 0x53525354) \
40+
IIF(RV32_HAS(SDL))( \
41+
_(draw_frame, 0xBEEF) \
42+
_(setup_queue, 0xC0DE) \
43+
_(submit_queue, 0xFEED) \
44+
_(setup_audio, 0xBABE) \
45+
_(control_audio, 0xD00D) \
4346
)
4447
/* clang-format on */
4548

@@ -369,6 +372,94 @@ extern void syscall_setup_audio(riscv_t *rv);
369372
extern void syscall_control_audio(riscv_t *rv);
370373
#endif
371374

375+
/* SBI related system calls */
376+
static void syscall_sbi_timer(riscv_t *rv)
377+
{
378+
vm_attr_t *attr = PRIV(rv);
379+
const riscv_word_t fid = rv_get_reg(rv, rv_reg_a6);
380+
const riscv_word_t a0 = rv_get_reg(rv, rv_reg_a0);
381+
const riscv_word_t a1 = rv_get_reg(rv, rv_reg_a1);
382+
383+
switch (fid) {
384+
case SBI_TIMER_SET_TIMER:
385+
attr->timer = (((uint64_t) a1) << 32) | (uint64_t) (a0);
386+
rv_set_reg(rv, rv_reg_a0, SBI_SUCCESS);
387+
rv_set_reg(rv, rv_reg_a1, 0);
388+
break;
389+
default:
390+
rv_set_reg(rv, rv_reg_a0, SBI_ERR_NOT_SUPPORTED);
391+
rv_set_reg(rv, rv_reg_a1, 0);
392+
break;
393+
}
394+
}
395+
396+
#define SBI_IMPL_ID 0x999
397+
#define SBI_IMPL_VERSION 1
398+
399+
static void syscall_sbi_base(riscv_t *rv)
400+
{
401+
const riscv_word_t fid = rv_get_reg(rv, rv_reg_a6);
402+
403+
switch (fid) {
404+
case SBI_BASE_GET_SBI_IMPL_ID:
405+
rv_set_reg(rv, rv_reg_a0, SBI_SUCCESS);
406+
rv_set_reg(rv, rv_reg_a1, SBI_IMPL_ID);
407+
break;
408+
case SBI_BASE_GET_SBI_IMPL_VERSION:
409+
rv_set_reg(rv, rv_reg_a0, SBI_SUCCESS);
410+
rv_set_reg(rv, rv_reg_a1, SBI_IMPL_VERSION);
411+
break;
412+
case SBI_BASE_GET_MVENDORID:
413+
rv_set_reg(rv, rv_reg_a0, SBI_SUCCESS);
414+
rv_set_reg(rv, rv_reg_a1, rv->csr_mvendorid);
415+
break;
416+
case SBI_BASE_GET_MARCHID:
417+
rv_set_reg(rv, rv_reg_a0, SBI_SUCCESS);
418+
rv_set_reg(rv, rv_reg_a1, rv->csr_marchid);
419+
break;
420+
case SBI_BASE_GET_MIMPID:
421+
rv_set_reg(rv, rv_reg_a0, SBI_SUCCESS);
422+
rv_set_reg(rv, rv_reg_a1, rv->csr_mimpid);
423+
break;
424+
case SBI_BASE_GET_SBI_SPEC_VERSION:
425+
rv_set_reg(rv, rv_reg_a0, SBI_SUCCESS);
426+
rv_set_reg(rv, rv_reg_a1, (0 << 24) | 3); /* version 0.3 */
427+
break;
428+
case SBI_BASE_PROBE_EXTENSION: {
429+
const riscv_word_t eid = rv_get_reg(rv, rv_reg_a0);
430+
bool available =
431+
eid == SBI_EID_BASE || eid == SBI_EID_TIMER || eid == SBI_EID_RST;
432+
rv_set_reg(rv, rv_reg_a0, SBI_SUCCESS);
433+
rv_set_reg(rv, rv_reg_a1, available);
434+
break;
435+
}
436+
default:
437+
rv_set_reg(rv, rv_reg_a0, SBI_ERR_NOT_SUPPORTED);
438+
rv_set_reg(rv, rv_reg_a1, 0);
439+
break;
440+
}
441+
}
442+
443+
static void syscall_sbi_rst(riscv_t *rv)
444+
{
445+
const riscv_word_t fid = rv_get_reg(rv, rv_reg_a6);
446+
const riscv_word_t a0 = rv_get_reg(rv, rv_reg_a0);
447+
const riscv_word_t a1 = rv_get_reg(rv, rv_reg_a1);
448+
449+
switch (fid) {
450+
case SBI_RST_SYSTEM_RESET:
451+
fprintf(stderr, "system reset: type=%u, reason=%u\n", a0, a1);
452+
rv_halt(rv);
453+
rv_set_reg(rv, rv_reg_a0, SBI_SUCCESS);
454+
rv_set_reg(rv, rv_reg_a1, 0);
455+
break;
456+
default:
457+
rv_set_reg(rv, rv_reg_a0, SBI_ERR_NOT_SUPPORTED);
458+
rv_set_reg(rv, rv_reg_a1, 0);
459+
break;
460+
}
461+
}
462+
372463
void syscall_handler(riscv_t *rv)
373464
{
374465
/* get the syscall number */

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