[AMDGPU] Enable NewPM for AMDGPU backend

vikramRH · vikramRH · commit a831fb4dbff3 · 2025-09-22T16:34:12.000+05:30
diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp
@@ -24,7 +24,9 @@
 #include "llvm/Bitcode/BitcodeReader.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
 #include "llvm/Bitcode/BitcodeWriterPass.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/Config/llvm-config.h"
 #include "llvm/Frontend/Driver/CodeGenOptions.h"
 #include "llvm/IR/DataLayout.h"
@@ -189,7 +191,12 @@ class EmitAssemblyHelper {
       std::unique_ptr<llvm::ToolOutputFile> &ThinLinkOS, BackendConsumer *BC);
   void RunCodegenPipeline(BackendAction Action,
                           std::unique_ptr<raw_pwrite_stream> &OS,
-                          std::unique_ptr<llvm::ToolOutputFile> &DwoOS);
+                          std::unique_ptr<llvm::ToolOutputFile> &DwoOS, 
+                          TargetMachine &TM);
+  void RunCodegenPipelineWithNewPM(BackendAction Action,
+                                  std::unique_ptr<raw_pwrite_stream> &OS,
+                                  std::unique_ptr<llvm::ToolOutputFile> &DwoOS, 
+                                  TargetMachine &TM);
 
   /// Check whether we should emit a module summary for regular LTO.
   /// The module summary should be emitted by default for regular LTO
@@ -1211,10 +1218,16 @@ void EmitAssemblyHelper::RunOptimizationPipeline(
 
 void EmitAssemblyHelper::RunCodegenPipeline(
     BackendAction Action, std::unique_ptr<raw_pwrite_stream> &OS,
-    std::unique_ptr<llvm::ToolOutputFile> &DwoOS) {
+    std::unique_ptr<llvm::ToolOutputFile> &DwoOS, TargetMachine &TM) {
   // We still use the legacy PM to run the codegen pipeline since the new PM
   // does not work with the codegen pipeline.
   // FIXME: make the new PM work with the codegen pipeline.
+
+  if (TM.EnableNewPMForBackend()) {
+      RunCodegenPipelineWithNewPM(Action, OS, DwoOS, TM);
+      return;
+  }
+      
   legacy::PassManager CodeGenPasses;
 
   // Append any output we need to the pass manager.
@@ -1259,6 +1272,74 @@ void EmitAssemblyHelper::RunCodegenPipeline(
   }
 }
 
+void EmitAssemblyHelper::RunCodegenPipelineWithNewPM(BackendAction Action, 
+    std::unique_ptr<raw_pwrite_stream> &OS,
+    std::unique_ptr<llvm::ToolOutputFile> &DwoOS, TargetMachine &TM) {
+  MachineModuleInfo MMI(&TM);
+  CGPassBuilderOption Opt = getCGPassBuilderOption();
+
+  Opt.DisableVerify = !CodeGenOpts.VerifyModule;
+  Opt.DebugPM = CodeGenOpts.DebugPassManager;
+
+  PassInstrumentationCallbacks PIC;
+  StandardInstrumentations SI(TheModule->getContext(), CodeGenOpts.DebugPassManager, 
+                              CodeGenOpts.VerifyEach);
+  registerCodeGenCallback(PIC, TM);
+
+  MachineFunctionAnalysisManager MFAM;
+  LoopAnalysisManager LAM;
+  FunctionAnalysisManager FAM;
+  CGSCCAnalysisManager CGAM;
+  ModuleAnalysisManager MAM;
+  PassBuilder PB(&TM, PipelineTuningOptions(), std::nullopt, &PIC);
+  
+  PB.registerModuleAnalyses(MAM);
+  PB.registerCGSCCAnalyses(CGAM);
+  PB.registerFunctionAnalyses(FAM);
+  PB.registerLoopAnalyses(LAM);
+  PB.registerMachineFunctionAnalyses(MFAM);
+  PB.crossRegisterProxies(LAM, FAM, CGAM, MAM, &MFAM);
+  SI.registerCallbacks(PIC, &MAM);
+    
+  TargetLibraryInfoImpl TLII(TheModule->getTargetTriple());
+
+  FAM.registerPass([&] { return TargetLibraryAnalysis(TLII); });
+  MAM.registerPass([&] { return MachineModuleAnalysis(MMI); });
+
+  ModulePassManager MPM;
+  FunctionPassManager FPM;
+
+  if (!TM.buildCodeGenPipeline(MPM, *OS, DwoOS ? &DwoOS->os() : nullptr,
+                                     getCodeGenFileType(Action), Opt, MMI.getContext(), &PIC)) {
+    Diags.Report(diag::err_fe_unable_to_interface_with_target);
+    return;
+  }
+  
+  if (PrintPipelinePasses) {
+    std::string PipelineStr;
+    raw_string_ostream OutS(PipelineStr);
+    MPM.printPipeline(OutS, [&PIC](StringRef ClassName) {
+      auto PassName = PIC.getPassNameForClassName(ClassName);
+      return PassName.empty() ? ClassName : PassName;
+    });
+    outs() << PipelineStr << '\n';
+    return;
+  }
+
+  {
+    PrettyStackTraceString CrashInfo("Code generation");
+    llvm::TimeTraceScope TimeScope("CodeGenPasses");
+    Timer timer;
+    if (CI.getCodeGenOpts().TimePasses) {
+      timer.init("codegen", "Machine code generation", CI.getTimerGroup());
+      CI.getFrontendTimer().yieldTo(timer);
+    }
+    MPM.run(*TheModule, MAM);
+    if (CI.getCodeGenOpts().TimePasses)
+      timer.yieldTo(CI.getFrontendTimer());
+  }  
+}
+
 void EmitAssemblyHelper::emitAssembly(BackendAction Action,
                                       std::unique_ptr<raw_pwrite_stream> OS,
                                       BackendConsumer *BC) {
@@ -1277,7 +1358,7 @@ void EmitAssemblyHelper::emitAssembly(BackendAction Action,
 
   std::unique_ptr<llvm::ToolOutputFile> ThinLinkOS, DwoOS;
   RunOptimizationPipeline(Action, OS, ThinLinkOS, BC);
-  RunCodegenPipeline(Action, OS, DwoOS);
+  RunCodegenPipeline(Action, OS, DwoOS, *TM);
 
   if (ThinLinkOS)
     ThinLinkOS->keep();
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -679,7 +679,7 @@ Error CodeGenPassBuilder<Derived, TargetMachineT>::buildPipeline(
       addPass(PrintMIRPass(Out), /*Force=*/true);
   }
 
-  {
+  if (PrintAsm) {
     AddIRPass addIRPass(MPM, derived());
     addIRPass(AsmPrinterFinalizePass(PrinterImpl));
   }
diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h
@@ -116,6 +116,7 @@ class LLVM_ABI TargetMachine {
 
   unsigned RequireStructuredCFG : 1;
   unsigned O0WantsFastISel : 1;
+  unsigned NewPMForBackend : 1;
 
   // PGO related tunables.
   std::optional<PGOOptions> PGOOption;
@@ -255,6 +256,9 @@ class LLVM_ABI TargetMachine {
   bool requiresStructuredCFG() const { return RequireStructuredCFG; }
   void setRequiresStructuredCFG(bool Value) { RequireStructuredCFG = Value; }
 
+  bool EnableNewPMForBackend() const { return NewPMForBackend; }
+  void setNewPMForBackend(bool Value) { NewPMForBackend = Value; }
+  
   /// Returns the code generation relocation model. The choices are static, PIC,
   /// and dynamic-no-pic, and target default.
   Reloc::Model getRelocationModel() const;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -751,6 +751,7 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
           getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
       TLOF(createTLOF(getTargetTriple())) {
   initAsmInfo();
+  setNewPMForBackend(true);
   if (TT.isAMDGCN()) {
     if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
       MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
diff --git a/llvm/lib/Target/TargetMachine.cpp b/llvm/lib/Target/TargetMachine.cpp
@@ -42,7 +42,7 @@ TargetMachine::TargetMachine(const Target &T, StringRef DataLayoutString,
     : TheTarget(T), DL(DataLayoutString), TargetTriple(TT),
       TargetCPU(std::string(CPU)), TargetFS(std::string(FS)), AsmInfo(nullptr),
       MRI(nullptr), MII(nullptr), STI(nullptr), RequireStructuredCFG(false),
-      O0WantsFastISel(false), Options(Options) {}
+      O0WantsFastISel(false), NewPMForBackend(false), Options(Options) {}
 
 TargetMachine::~TargetMachine() = default;
 
diff --git a/llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir b/llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir
@@ -1,7 +1,7 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass postrapseudos -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX900,NOT-GFX1250 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass postrapseudos -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX90A,NOT-GFX1250 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -run-pass postrapseudos -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX942,NOT-GFX1250 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass postrapseudos %s -o - | FileCheck -check-prefixes=GCN,GFX1250 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes="post-ra-pseudos" -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX900,NOT-GFX1250 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -passes="post-ra-pseudos" -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX90A,NOT-GFX1250 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -passes="post-ra-pseudos" -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX942,NOT-GFX1250 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -passes="post-ra-pseudos" %s -o - | FileCheck -check-prefixes=GCN,GFX1250 %s
 
 # GCN-LABEL: name: v_mov_b64_from_vgpr
 # GFX900: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit-def $vgpr0_vgpr1
diff --git a/llvm/tools/llc/llc.cpp b/llvm/tools/llc/llc.cpp
@@ -655,7 +655,8 @@ static int compileModule(char **argv, LLVMContext &Context) {
   else if (VerifyEach)
     VK = VerifierKind::EachPass;
 
-  if (EnableNewPassManager || !PassPipeline.empty()) {
+  if (EnableNewPassManager || !PassPipeline.empty() ||
+      Target->EnableNewPMForBackend()) {
     return compileModuleWithNewPM(argv[0], std::move(M), std::move(MIR),
                                   std::move(Target), std::move(Out),
                                   std::move(DwoOut), Context, TLII, VK,

Original file line number	Diff line number	Diff line change
`@@ -679,7 +679,7 @@ Error CodeGenPassBuilder<Derived, TargetMachineT>::buildPipeline(`
`679`	`679`	`addPass(PrintMIRPass(Out), /Force=/true);`
`680`	`680`	`}`
`681`	`681`
`682`		`- {`
	`682`	`+ if (PrintAsm) {`
`683`	`683`	`AddIRPass addIRPass(MPM, derived());`
`684`	`684`	`addIRPass(AsmPrinterFinalizePass(PrinterImpl));`
`685`	`685`	`}`