Merge branch 'master' into aic8800_flash_driver

Author: talpachen

LICENSES/preferred/CC0-1.0

@@ -0,0 +1,130 @@
+Valid-License-Identifier: CC0-1.0
+SPDX-URL: https://spdx.org/licenses/CC0-1.0.html
+Usage-Guide:
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+    SPDX-License-Identifier: CC0-1.0
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Makefile.am

@@ -64,6 +64,7 @@ EXTRA_DIST += \
 	LICENSES/preferred/BSD-2-Clause-Views \
 	LICENSES/preferred/BSD-3-Clause \
 	LICENSES/preferred/BSD-Source-Code \
+	LICENSES/preferred/CC0-1.0 \
 	LICENSES/preferred/GFDL-1.2 \
 	LICENSES/preferred/gfdl-1.2.texi.readme \
 	LICENSES/preferred/GPL-2.0 \

contrib/firmware/angie/c/include/i2c.h

@@ -19,6 +19,7 @@ void repeated_start(void);
 void stop_cd(void);
 void clock_cd(void);
 void send_ack(void);
+void send_nack(void);
 bool get_ack(void);
 
 uint8_t get_address(uint8_t adr, uint8_t rdwr);

contrib/firmware/angie/c/src/i2c.c

@@ -60,6 +60,16 @@ void send_ack(void)
 	delay_us(1);
 }
 
+void send_nack(void)
+{
+	PIN_SDA = 1;
+	delay_us(1);
+	PIN_SCL = 1;
+	delay_us(1);
+	PIN_SCL = 0;
+	delay_us(1);
+}
+
 bool get_ack(void)
 {
 	PIN_SDA_DIR = 1;

contrib/firmware/angie/c/src/usb.c

@@ -757,14 +757,13 @@ void i2c_recieve(void)
 	PIN_SDA_DIR = 0;
 	if (EP6FIFOBUF[0] == 1) {
 		uint8_t rdwr = EP6FIFOBUF[0];   //read
-		uint8_t reg_adr_check = EP6FIFOBUF[1];
-		uint8_t count = EP6FIFOBUF[2];  //request data count
+		uint8_t data_count = EP6FIFOBUF[1]; //data sent count
+		uint8_t count = EP6FIFOBUF[2];  //requested data count
 		uint8_t adr = EP6FIFOBUF[3];    //address
-		uint8_t reg_adr = EP6FIFOBUF[4];
 		uint8_t address = get_address(adr, rdwr);   //address byte (read command)
 		uint8_t address_2 = get_address(adr, 0);   //address byte 2 (write command)
 
-		printf("%d\n", address);
+		printf("%d\n", address - 1);
 
 		/*  start:   */
 		start_cd();
@@ -773,41 +772,38 @@ void i2c_recieve(void)
 		/*  ack:  */
 		uint8_t ack = get_ack();
 
-		delay_us(10);
-
 		/*   send data   */
-		if (reg_adr_check) { //if there is a byte reg
-			send_byte(reg_adr);
-			/*  ack():  */
-			ack = get_ack();
+		if (data_count) { //if there is a byte reg
+			for (uint8_t i = 0; i < data_count; i++) {
+				send_byte(EP6FIFOBUF[i + 4]);
+				/*  ack():  */
+				ack = get_ack();
+			}
 		}
 
-		delay_us(10);
-
 		/*  repeated start:  */
 		repeated_start();
 		/*  address:   */
 		send_byte(address);
 		/*  get ack:  */
 		ack = get_ack();
 
-		delay_us(10);
-
 		/*   receive data   */
-		for (uint8_t i = 0; i < count; i++) {
+		for (uint8_t i = 0; i < count - 1; i++) {
 			EP8FIFOBUF[i] = receive_byte();
 
-			/*  send ack:  */
+			/*  send ack: */
 			send_ack();
 		}
 
-		delay_ms(1);
+		EP8FIFOBUF[count - 1] = receive_byte();
+
+		/*  send Nack:  */
+		send_nack();
 
 		/*   stop   */
 		stop_cd();
 
-		delay_us(10);
-
 		EP8BCH = 0; //EP8
 		syncdelay(3);
 		EP8BCL = count; //EP8

contrib/rtos-helpers/FreeRTOS-openocd.c

@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-License-Identifier: CC0-1.0
 
 /*
  * Since at least FreeRTOS V7.5.3 uxTopUsedPriority is no longer

doc/openocd.texi

@@ -2543,27 +2543,27 @@ and a specific set of GPIOs is used.
 ARM CMSIS-DAP compliant based adapter v1 (USB HID based)
 or v2 (USB bulk).
 
-@deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
+@deffn {Config Command} {cmsis-dap vid_pid} [vid pid]+
 The vendor ID and product ID of the CMSIS-DAP device. If not specified
 the driver will attempt to auto detect the CMSIS-DAP device.
 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
 @example
-cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
+cmsis-dap vid_pid 0xc251 0xf001 0x0d28 0x0204
 @end example
 @end deffn
 
-@deffn {Config Command} {cmsis_dap_backend} [@option{auto}|@option{usb_bulk}|@option{hid}]
+@deffn {Config Command} {cmsis-dap backend} [@option{auto}|@option{usb_bulk}|@option{hid}]
 Specifies how to communicate with the adapter:
 
 @itemize @minus
 @item @option{hid} Use HID generic reports - CMSIS-DAP v1
 @item @option{usb_bulk} Use USB bulk - CMSIS-DAP v2
 @item @option{auto} First try USB bulk CMSIS-DAP v2, if not found try HID CMSIS-DAP v1.
-This is the default if @command{cmsis_dap_backend} is not specified.
+This is the default if @command{cmsis-dap backend} is not specified.
 @end itemize
 @end deffn
 
-@deffn {Config Command} {cmsis_dap_usb interface} [number]
+@deffn {Config Command} {cmsis-dap usb interface} [number]
 Specifies the @var{number} of the USB interface to use in v2 mode (USB bulk).
 In most cases need not to be specified and interfaces are searched by
 interface string or for user class interface.
@@ -2991,7 +2991,7 @@ This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
 families, but it is possible to use it with some other devices. If you are using
 this adapter with a PSoC or a PRoC, you may need to add
-@command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
+@command{kitprog init_acquire_psoc} or @command{kitprog acquire_psoc} to your
 configuration script.
 
 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
@@ -3012,14 +3012,14 @@ versions only implement "SWD line reset". Second, due to a firmware quirk, an
 SWD sequence must be sent after every target reset in order to re-establish
 communications with the target.
 @item Due in part to the limitation above, KitProg devices with firmware below
-version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
+version 2.14 will need to use @command{kitprog init_acquire_psoc} in order to
 communicate with PSoC 5LP devices. This is because, assuming debug is not
 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
 could only be sent with an acquisition sequence.
 @end itemize
 
-@deffn {Config Command} {kitprog_init_acquire_psoc}
+@deffn {Config Command} {kitprog init_acquire_psoc}
 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
 Please be aware that the acquisition sequence hard-resets the target.
 @end deffn
@@ -5296,6 +5296,18 @@ Displays the current target state:
 (Also, @pxref{eventpolling,,Event Polling}.)
 @end deffn
 
+@deffn {Command} {$target_name debug_reason}
+Displays the current debug reason:
+@code{debug-request},
+@code{breakpoint},
+@code{watchpoint},
+@code{watchpoint-and-breakpoint},
+@code{single-step},
+@code{target-not-halted},
+@code{program-exit},
+@code{exception-catch} or @code{undefined}.
+@end deffn
+
 @deffn {Command} {$target_name eventlist}
 Displays a table listing all event handlers
 currently associated with this target.
@@ -9436,8 +9448,9 @@ Return a list of all channels and their properties as Tcl list.
 The list can be manipulated easily from within scripts.
 @end deffn
 
-@deffn {Command} {rtt server start} port channel
-Start a TCP server on @var{port} for the channel @var{channel}.
+@deffn {Command} {rtt server start} port channel [message]
+Start a TCP server on @var{port} for the channel @var{channel}. When
+@var{message} is not empty, it will be sent to a client when it connects.
 @end deffn
 
 @deffn {Command} {rtt server stop} port
@@ -11352,16 +11365,18 @@ NOTE: @file{xtensa-core-XXX.cfg} must match the target Xtensa hardware
 connected to OpenOCD.
 
 Some example Xtensa configurations are bundled with OpenOCD for reference:
-@itemize @bullet
+@enumerate
 @item Cadence Palladium VDebug emulation target. The user can combine their
 @file{xtensa-core-XXX.cfg} with the provided
 @file{board/xtensa-palladium-vdebug.cfg} to debug an emulated Xtensa RTL design.
-@item NXP MIMXRT685-EVK evaluation kit. The relevant configuration files are
-@file{board/xtensa-rt685-jlink.cfg} and @file{board/xtensa-core-nxp_rt600.cfg}.
-Additional information is provided by
-@uref{https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt600-evaluation-kit:MIMXRT685-EVK,
-NXP}.
+@item NXP MIMXRT685-EVK evaluation kit. The relevant configuration files are:
+@itemize @bullet
+@item @file{board/xtensa-rt685-ext.cfg}
+@item @file{target/xtensa-core-nxp_rt600.cfg}
 @end itemize
+Additional information is available by searching for "i.MX RT600 Evaluation Kit"
+on @url{https://www.nxp.com}.
+@end enumerate
 
 @subsection Xtensa Configuration Commands
 
@@ -11386,6 +11401,11 @@ others may be common to both but have different valid ranges.
 Configure Xtensa target memory. Memory type determines access rights,
 where RAMs are read/write while ROMs are read-only. @var{baseaddr} and
 @var{bytes} are both integers, typically hexadecimal and decimal, respectively.
+
+NOTE: Some Xtensa memory types, such as system RAM/ROM or MMIO/device regions,
+can be added or modified after the Xtensa core has been generated. Additional
+@code{xtensa xtmem} definitions should be manually added to xtensa-core-XXX.cfg
+to keep OpenOCD's target address map consistent with the Xtensa configuration.
 @end deffn
 
 @deffn {Config Command} {xtensa xtmem} (@option{icache}|@option{dcache}) linebytes cachebytes ways [writeback]
@@ -11468,6 +11488,12 @@ Execute arbitrary instruction(s) provided as an ascii string.  The string repres
 number of instruction bytes, thus its length must be even.
 @end deffn
 
+@deffn {Command} {xtensa dm} (address) [value]
+Read or write Xtensa Debug Module (DM) registers.  @var{address} is required for both reads
+and writes and is a 4-byte-aligned value typically between 0 and 0x3ffc.  @var{value} is specified
+only for write accesses.
+@end deffn
+
 @subsection Xtensa Performance Monitor Configuration
 
 @deffn {Command} {xtensa perfmon_enable} <counter_id> <select> [mask] [kernelcnt] [tracelevel]