Merge branch 'RT_reorganization' into 'develop'

Rt reorganization

See merge request racetrack-logic/risc-v-lim-architecture!11

Author: f-riente

RI5CY-sameIF/tb/core/Makefile

@@ -60,25 +60,26 @@ VERI_CFLAGS             = -O2
 
 # RTL source files
 RTLSRC_HOME             := ../..
-RTLSRC_TB_PKG		:=
-RTLSRC_TB_TOP		:= tb_top.sv
-RTLSRC_TB		:= $(filter-out riscv_tb_pkg.sv tb_top_verilator.sv,\
-				$(wildcard *.sv))
+RTLSRC_TB_PKG           :=
+RTLSRC_TB_TOP           := tb_top.sv
+RTLSRC_TB               := $(filter-out riscv_tb_pkg.sv tb_top_verilator.sv,\
+                            $(wildcard *.sv))
+RTLSRC_TB_RT            := $(wildcard ./RT_rtl/*.sv)
 RTLSRC_VERI_TB          := $(filter-out tb_top.sv, $(wildcard *.sv))
 RTLSRC_INCDIR           := $(RTLSRC_HOME)/rtl/include
-RTLSRC_PKG		:= $(RTLSRC_HOME)/rtl/fpnew/src/fpnew_pkg.sv \
-				$(addprefix $(RTLSRC_HOME)/rtl/include/,\
-				apu_core_package.sv riscv_defines.sv \
-				riscv_tracer_defines.sv ../../tb/tb_riscv/include/perturbation_defines.sv)
-RTLSRC			:= $(filter-out $(RTLSRC_HOME)/rtl/riscv_register_file_latch.sv,\
-				$(wildcard $(RTLSRC_HOME)/rtl/*.sv) $(RTLSRC_HOME)/tb/tb_riscv/riscv_random_stall.sv $(RTLSRC_HOME)/tb/tb_riscv/riscv_random_interrupt_generator.sv)
-RTLSRC_FPNEW_INCDIR := $(RTLSRC_HOME)/rtl/fpnew/src/common_cells/include
-RTLSRC_FPNEWPKG     := $(RTLSRC_HOME)/rtl/fpnew/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
-RTLSRC_FPNEW        := $(wildcard $(RTLSRC_HOME)/rtl/fpnew/src/*.sv) $(wildcard $(RTLSRC_HOME)/rtl/fpnew/src/fpu_div_sqrt_mvp/hdl/*.sv) \
-                    $(wildcard $(RTLSRC_HOME)/rtl/fpnew/src/common_cells/src/*.sv) $(wildcard $(RTLSRC_HOME)/rtl/fpnew/src/common_cells/src/deprecated/*.sv)
+RTLSRC_PKG              := $(RTLSRC_HOME)/rtl/fpnew/src/fpnew_pkg.sv \
+                            $(addprefix $(RTLSRC_HOME)/rtl/include/,\
+                            apu_core_package.sv riscv_defines.sv \
+                            riscv_tracer_defines.sv ../../tb/tb_riscv/include/perturbation_defines.sv)
+RTLSRC                  := $(filter-out $(RTLSRC_HOME)/rtl/riscv_register_file_latch.sv,\
+                            $(wildcard $(RTLSRC_HOME)/rtl/*.sv) $(RTLSRC_HOME)/tb/tb_riscv/riscv_random_stall.sv $(RTLSRC_HOME)/tb/tb_riscv/riscv_random_interrupt_generator.sv)
+RTLSRC_FPNEW_INCDIR     := $(RTLSRC_HOME)/rtl/fpnew/src/common_cells/include
+RTLSRC_FPNEWPKG         := $(RTLSRC_HOME)/rtl/fpnew/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
+RTLSRC_FPNEW            := $(wildcard $(RTLSRC_HOME)/rtl/fpnew/src/*.sv) $(wildcard $(RTLSRC_HOME)/rtl/fpnew/src/fpu_div_sqrt_mvp/hdl/*.sv) \
+                            $(wildcard $(RTLSRC_HOME)/rtl/fpnew/src/common_cells/src/*.sv) $(wildcard $(RTLSRC_HOME)/rtl/fpnew/src/common_cells/src/deprecated/*.sv)
 # TODO: clean this up
-RTLSRC_VLOG_TB_TOP	:= $(basename $(notdir $(RTLSRC_TB_TOP)))
-RTLSRC_VOPT_TB_TOP	:= $(RTLSRC_VLOG_TB_TOP)#$(addsuffix _vopt, $(RTLSRC_VLOG_TB_TOP))
+RTLSRC_VLOG_TB_TOP      := $(basename $(notdir $(RTLSRC_TB_TOP)))
+RTLSRC_VOPT_TB_TOP      := $(RTLSRC_VLOG_TB_TOP)#$(addsuffix _vopt, $(RTLSRC_VLOG_TB_TOP))
 
 # riscv toolchain install path
 RISCV_LIB               ?= <tool_chain_install_path>
@@ -136,9 +137,9 @@ vlib: .lib-rtl
 	touch .lib-rtl
 
 # rebuild if we change some sourcefile
-.build-rtl: .lib-rtl $(RTLSRC_PKG) $(RTLSRC) $(RTLSRC_TB_PKG) $(RTLSRC_TB)
+.build-rtl: .lib-rtl $(RTLSRC_PKG) $(RTLSRC) $(RTLSRC_TB_PKG) $(RTLSRC_TB) $(RTLSRC_TB_RT)
 	$(VLOG) +define+$(MEM_TYPE) -work $(VWORK) +incdir+$(RTLSRC_INCDIR) $(VLOG_FLAGS) \
-	$(RTLSRC_PKG) $(RTLSRC) $(RTLSRC_TB_PKG) $(RTLSRC_TB)
+	$(RTLSRC_PKG) $(RTLSRC) $(RTLSRC_TB_PKG) $(RTLSRC_TB) $(RTLSRC_TB_RT)
 	touch .build-rtl
 
 vsim-all: .build-rtl
@@ -149,9 +150,9 @@ vsim-all: .build-rtl
 	touch .opt-rtl
 
 # rebuild if we change some sourcefile
-.build-rtl-fp: .lib-rtl $(RTLSRC_PKG) $(RTLSRC_FPNEWPKG) $(RTLSRC_FPNEW) $(RTLSRC) $(RTLSRC_TB_PKG) $(RTLSRC_TB)
+.build-rtl-fp: .lib-rtl $(RTLSRC_PKG) $(RTLSRC_FPNEWPKG) $(RTLSRC_FPNEW) $(RTLSRC) $(RTLSRC_TB_PKG) $(RTLSRC_TB) $(RTLSRC_TB_RT)
 	$(VLOG) -work $(VWORK) +incdir+$(RTLSRC_INCDIR) +incdir+$(RTLSRC_FPNEW_INCDIR) $(VLOG_FLAGS) \
-	$(RTLSRC_PKG) $(RTLSRC_FPNEWPKG) $(RTLSRC_FPNEW) $(RTLSRC) $(RTLSRC_TB_PKG) $(RTLSRC_TB)
+	$(RTLSRC_PKG) $(RTLSRC_FPNEWPKG) $(RTLSRC_FPNEW) $(RTLSRC) $(RTLSRC_TB_PKG) $(RTLSRC_TB) $(RTLSRC_TB_RT)
 	touch .build-rtl-fp
 
 vsim-all-fp: .opt-rtl-fp
@@ -170,11 +171,11 @@ dpiheader: .build-tb
 # ===================================================================
 #ORIGIANL TIMESCALE -timescale=1ns/1ps 
 
-vcsify: $(RTLSRC_PKG) $(RTLSRC) $(RTLSRC_TB_PKG) $(RTLSRC_TB)
+vcsify: $(RTLSRC_PKG) $(RTLSRC) $(RTLSRC_TB_PKG) $(RTLSRC_TB) $(RTLSRC_TB_RT)
 	$(VCS) +vc -sverilog -race=all -ignore unique_checks -full64 \
 		-timescale=1ns/1ns -j20\
 		-CC "-I$(VCS_HOME)/include -O3 -march=native" $(VCS_FLAGS) \
-		$(RTLSRC_PKG) $(RTLSRC) $(RTLSRC_TB_PKG) $(RTLSRC_TB) \
+		$(RTLSRC_PKG) $(RTLSRC) $(RTLSRC_TB_PKG) $(RTLSRC_TB) $(RTLSRC_TB_RT)\
 		+incdir+$(RTLSRC_INCDIR) +define+$(MEM_TYPE)
 
 #STANDARD PROGRAMS (MEM_TYPE=STD_MEM)

RI5CY-sameIF/tb/core/FSM.sv renamed to RI5CY-sameIF/tb/core/RT_rtl/FSM.sv

@@ -0,0 +1,38 @@
+Racetrack memory RTL model
+==========================
+This folder contains all the RTL files of the Racetrack memory.
+
+Memory organization
+--------------------------
+In the following a brief insight of the hierarchical architecture of the memory will be given.
+The Racetrack memory array is made up by multiple basic elements called Blocks, the required number of Blocks is istantiated automatically based on the memory size. The file `RT_memory` intantiates the required number of Blocks based on the memory parameters.
+Each block is internally divided in multiple Macro Units, 32x32 bits arrays composed by several Racetracks. The file `RT_block` instantiates the required number of Macro Units based on the memory parameters, then hierarchically the file `RT_32_8_4_MU` instantiates all the required Racetracks.
+The Racetrack has a 3D structure composed by four different Racetracks:
+* Logic Racetrack : computes and stores LiM results
+* Data Racetrack : stores standard Data
+* Mask Racetrack : stores Mask values
+* Program Racetrack : stores program bit 
+
+The file `RT_32_8_4_line` instantiates all the basic Racetrack cells (`pNML_NAND_NOR`, `pNML_NAND_NOR_SOT`, `RT_cell`, `RT_read_write_SOT`) for each of the four different Racetracks.
+
+<img src="./images/RT_32_8_4_profile_3D.png" align="center" width="80%" height="80%">
+
+Memory architecture
+--------------------------
+The Racetrack array is instantiaed in the file `RT_memory`, which wraps the raw memory core and adds surrounding logic for the correct functioning (i.e. `FSM` and `shifter` modules), this module includes also all the logic required for the LiM computations. 
+
+<img src="./images/racetrack_array_arch.png" align="center" width="50%" height="50%">
+
+The Racetrack memory is instantiated by the file `dp_ram_logic`, which provides all the additional logic (i.e. decoders, shift number generator etc.).
+
+<img src="./images/racetrack_memory_arch.png" align="center" width="50%" height="50%">
+
+Word organization
+--------------------------
+The Racetrack memory is capable of parallel LiM store operations by performing parallel accesses in each Block. This feature requires a different word organizayion within the memory.
+
+<img src="./images/word_organization.png" align="center" width="25%" height="25%">
+
+
+
+