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f-riente · f-riente · commit f2e2f4c94816 · 2022-03-15T11:47:01.000+01:00
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 # RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures
 
 The aim of the project is to propose a RISC-Vlim microprocessor that supports Logic-in-Memory operations. The RISC-Vlim is based on the RISC-V ISA where the data memory is replaced with a memory capable of doing simple operations on the data stored inside it. The preliminary results demonstrate how the use of such memories can improve the algorithm execution speed, reducing the need of complex solutions and saving energy.\

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`1`	`3`	`# RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures`
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`3`	`5`	`The aim of the project is to propose a RISC-Vlim microprocessor that supports Logic-in-Memory operations. The RISC-Vlim is based on the RISC-V ISA where the data memory is replaced with a memory capable of doing simple operations on the data stored inside it. The preliminary results demonstrate how the use of such memories can improve the algorithm execution speed, reducing the need of complex solutions and saving energy.\`