@@ -850,11 +850,10 @@ def load_order_modules(self) -> Iterable[interfaces.objects.ObjectInterface]:
850850 )
851851 peb .Ldr = peb .Ldr .cast ("pointer" , subtype = ldr_data )
852852 sym_table = self ._32bit_table_name
853- for entry in peb .Ldr .InLoadOrderModuleList .to_list (
853+ yield from peb .Ldr .InLoadOrderModuleList .to_list (
854854 f"{ sym_table } { constants .BANG } " + "_LDR_DATA_TABLE_ENTRY" ,
855855 "InLoadOrderLinks" ,
856- ):
857- yield entry
856+ )
858857 except exceptions .InvalidAddressException :
859858 return None
860859
@@ -875,11 +874,10 @@ def init_order_modules(self) -> Iterable[interfaces.objects.ObjectInterface]:
875874 )
876875 peb .Ldr = peb .Ldr .cast ("pointer" , subtype = ldr_data )
877876 sym_table = self ._32bit_table_name
878- for entry in peb .Ldr .InInitializationOrderModuleList .to_list (
877+ yield from peb .Ldr .InInitializationOrderModuleList .to_list (
879878 f"{ sym_table } { constants .BANG } " + "_LDR_DATA_TABLE_ENTRY" ,
880879 "InInitializationOrderLinks" ,
881- ):
882- yield entry
880+ )
883881 except exceptions .InvalidAddressException :
884882 return None
885883
@@ -899,11 +897,10 @@ def mem_order_modules(self) -> Iterable[interfaces.objects.ObjectInterface]:
899897 )
900898 peb .Ldr = peb .Ldr .cast ("pointer" , subtype = ldr_data )
901899 sym_table = self ._32bit_table_name
902- for entry in peb .Ldr .InMemoryOrderModuleList .to_list (
900+ yield from peb .Ldr .InMemoryOrderModuleList .to_list (
903901 f"{ sym_table } { constants .BANG } " + "_LDR_DATA_TABLE_ENTRY" ,
904902 "InMemoryOrderLinks" ,
905- ):
906- yield entry
903+ )
907904 except exceptions .InvalidAddressException :
908905 return None
909906
0 commit comments