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Commit 4fd19ae

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Fix memory functions
1 parent e74f9c2 commit 4fd19ae

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2 files changed

+5
-8
lines changed

2 files changed

+5
-8
lines changed

riscvmodel/model.py

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -83,16 +83,13 @@ def changes(self):
8383

8484
def commit(self):
8585
for update in self.memory_updates:
86-
address = update[1]
86+
address = update.addr
8787
base = address >> 2
8888
offset = address & 0x3
8989
if base not in self.memory:
9090
self.memory[base] = randrange(0, 1 << 32)
91-
data = update[2]
92-
if update[0] == 1:
93-
mask = ~(0xFF << (offset*8)) & 0xFFFFFFFF
94-
data = (self.memory[base] & mask) | (data << (offset*8))
95-
elif update[0] == 2:
91+
data = update.data
92+
if update.gran == TraceMemory.GRANULARITY.BYTE:
9693
mask = ~(0xFF << (offset*8)) & 0xFFFFFFFF
9794
data = (self.memory[base] & mask) | (data << (offset*8))
9895
self.memory[base] = data
@@ -135,4 +132,4 @@ def check(self, traces, exp=None):
135132
if isinstance(t, TraceIntegerRegister):
136133
if int(self.state.intreg[t.id]) != int(t.value):
137134
return False
138-
return True
135+
return True

riscvmodel/variant.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,4 +24,4 @@
2424
RV64IMAFD = Variant(intregs=32, xlen=64, extensions = Extensions(M=True, A=True, F=True, D=True))
2525
RV64G = RV64IMAFD
2626
RV64IMAFDC = Variant(intregs=32, xlen=64, extensions = Extensions(M=True, A=True, F=True, D=True, C=True))
27-
RV64GC = RV64IMAFDC
27+
RV64GC = RV64IMAFDC

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