Merge pull request riscv-non-isa#92 from lenary/pr/inline-asm

Inline Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs

Author: kito-cheng

src/c-api.adoc

@@ -732,11 +732,17 @@ Sign extension of 32-bit values on RV64 is not reflected in the interface.
 
 This section lists operand constraints that can be used with inline assembly
 statements, including both RISC-V specific and common operand constraints.
+Operand constraints are case-sensitive.
+
+"Floating-point register" in both the `f` and `cf` rows means "a register
+suitable for passing a floating-point value", so when using the `Zfinx`,
+`Zdinx`, or `Zhinxmin` extensions this will allocate an X register. This is done
+to aid portability of floating-point code.
 
 .Constraints on Operands of Inline Assembly Statements
 [%autowidth]
 |===
-|*Constraint*       |                                             |*Note*
+|*Constraint*       |*Description*                                |*Note*
 |m                  |An address that is held in a general-purpose register with offset. |
 |A                  |An address that is held in a general-purpose register. |
 |r                  |General purpose register                     |
@@ -746,13 +752,25 @@ statements, including both RISC-V specific and common operand constraints.
 |K                  |5-bit unsigned immediate integer operand     |
 |J                  |Zero integer immediate operand               |
 |s                  |symbol or label reference with a constant offset |
+|cr                 |RVC general purpose register (`x8`-`x15`)  |
+|cf                 |RVC floating-point register (`f8`-`f15` or `x8-x15` with `Zfinx`) |
+|R                  |Even-odd general purpose register pair     |
 |vr                 |Vector register                    |
 |vd                 |Vector register, excluding v0      |
 |vm                 |Vector register, only v0           |
 |===
 
+The `R` constraint should print as the even register in the pair, as this
+matches how the `amocas.q` instruction (on RV64) or the `amocas.d` and `Zdinx`
+instructions (on RV32) expect to parse their pair register operands. However,
+both registers in the pair should be considered to be live or clobbered
+together.
+
 NOTE: Immediate value must be a compile-time constant.
 
+NOTE: The `c*` constraints are designed to be extensible to more kinds of
+RVC-compatible register constraints in the future.
+
 === The Difference Between `m` and `A` Constraints
 
 The difference between `m` and `A` is whether the operand can have an offset;
@@ -809,6 +827,7 @@ statements, including both RISC-V specific and common operand modifiers.
 |*Modifiers*       |*Description*                                                                  |*Note*
 |z            |Print `zero` (`x0`) register for immediate 0, typically used with constraints `J` |
 |i            |Print `i` if corresponding operand is immediate.                                  |
+|N            |Print register encoding as integer (0-31). |
 |===
 
 [id=function-multi-version]