[Tricore]: Fixed i32.load16_s and i32.load16_u producing incorrect results with unaligned addresses due to shared load cache between signed and unsigned variants (#748)

Author: Changqing-JING

RELEASENOTES.md

@@ -1,5 +1,8 @@
 # Wasm Compiler Release Notes
 
+## 3.0.10
+- TriCore backend: Fixed i32.load16_s and i32.load16_u producing incorrect results with unaligned addresses due to shared load cache between signed and unsigned variants 
+
 ## 3.0.9
 - x86_64 backend: fix wrong register selection of f32/f64 max/min.
 
@@ -76,6 +79,7 @@
 - Stop supporting of tc1.6 and only support tc1.8
 
 ## Release v2 known issues
+- [Bug fixed by 3.0.10](#3010)
 - [Bug fixed by 3.0.9](#309)
 - [Bug fixed by 3.0.4](#304)
 

src/core/compiler/backend/tricore/tricore_backend.cpp

@@ -2113,9 +2113,10 @@ StackElement Backend::executeLinearMemoryLoad(OPCode const opcode, uint32_t cons
     RelPatchObj const end{as_.INSTR(J_disp24sx2).prepJmp()};
     unaligned.linkToHere();
     { // Unaligned
-      if (unalignedAccessCodePositions_.load2 == UINT32_MAX) {
+      uint32_t &load2PosRef{signExtend ? unalignedAccessCodePositions_.load2s : unalignedAccessCodePositions_.load2u};
+      if (load2PosRef == UINT32_MAX) {
         RelPatchObj const skip{as_.INSTR(J_disp24sx2).prepJmp()};
-        unalignedAccessCodePositions_.load2 = output_.size();
+        load2PosRef = output_.size();
         // Push register to the stack
         constexpr REG helperReg{REG::D15};
         as_.INSTR(STW_deref_Ab_off10sx_Da_preinc).setAb(REG::SP).setOff10sx(SafeInt<10>::fromConst<-4>()).setDa(helperReg)();
@@ -2136,7 +2137,7 @@ StackElement Backend::executeLinearMemoryLoad(OPCode const opcode, uint32_t cons
         skip.linkToHere();
       }
 
-      as_.INSTR(FCALL_disp24sx2).prepJmp().linkToBinaryPos(unalignedAccessCodePositions_.load2);
+      as_.INSTR(FCALL_disp24sx2).prepJmp().linkToBinaryPos(load2PosRef);
       as_.INSTR(MOVD_Da_Ab).setDa(targetRegElem.reg).setAb(WasmABI::REGS::memLdStReg)();
     }
     end.linkToHere();

src/core/compiler/backend/tricore/tricore_backend.hpp

@@ -733,9 +733,10 @@ class Tricore_Backend final {
   /// @brief Positions of where the logic for unaligned memory load/store is, can be reused by later code to save space
   class UnalignedAccessCodePositions final {
   public:
-    uint32_t load2 = UINT32_MAX; ///< Position of unaligned load 2 bytes memory access
-    uint32_t load4 = UINT32_MAX; ///< Position of unaligned load 4 bytes memory access
-    uint32_t load8 = UINT32_MAX; ///< Position of unaligned load 8 bytes memory access
+    uint32_t load2s = UINT32_MAX; ///< Position of unaligned load 2 signed bytes memory access
+    uint32_t load2u = UINT32_MAX; ///< Position of unaligned load 2 unsigned bytes memory access
+    uint32_t load4 = UINT32_MAX;  ///< Position of unaligned load 4 bytes memory access
+    uint32_t load8 = UINT32_MAX;  ///< Position of unaligned load 8 bytes memory access
 
     uint32_t store2 = UINT32_MAX; ///< Position of unaligned store 2 bytes memory access
     uint32_t store4 = UINT32_MAX; ///< Position of unaligned store 4 bytes memory access

tests/testsuite/vb_tricore_load16.wast

@@ -0,0 +1,19 @@
+(module
+  (memory 1)
+  
+  (data (i32.const 100) "\ff\7f\80\00\ff\ff\00\80\00\00\00\00\ff\ff\ff\7f")
+  
+  (func (export "i32_load16_s_misaligned") (result i32)
+    i32.const 0
+    i32.load16_s offset=101
+  )
+  
+  (func (export "i32_load16_u_misaligned") (result i32)
+    i32.const 101
+    i32.load16_u 
+  )
+)
+
+(assert_return (invoke "i32_load16_u_misaligned") (i32.const 32895))
+
+