Update wasmi_ir2 (#1660)

* fix identifiers for signed v128 prefixes

* remove non-existing simd ops

* fix some ternary relaxed SIMD operators

* clean-up and simplify UnaryOp[Kind] codegen

* feature guard TernaryOp and impls

Author: Robbepop

crates/ir2/build/display/constructors.rs

@@ -12,6 +12,7 @@ use crate::build::{
         StoreOp,
         TableGetOp,
         TableSetOp,
+        TernaryOp,
         UnaryOp,
         V128LoadLaneOp,
         V128ReplaceLaneOp,
@@ -101,6 +102,7 @@ macro_rules! impl_display_constructor {
 impl_display_constructor! {
     UnaryOp,
     BinaryOp,
+    TernaryOp,
     CmpBranchOp,
     CmpSelectOp,
     LoadOp,

crates/ir2/build/display/decode.rs

@@ -16,6 +16,7 @@ use crate::build::{
         StoreOp,
         TableGetOp,
         TableSetOp,
+        TernaryOp,
         UnaryOp,
         V128LoadLaneOp,
         V128ReplaceLaneOp,
@@ -74,6 +75,17 @@ impl Display for DisplayDecode<&'_ BinaryOp> {
     }
 }
 
+impl Display for DisplayDecode<&'_ TernaryOp> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let op = self.value;
+        let camel_ident = DisplayIdent::camel(op);
+        let a = op.a_field().ty;
+        let b = op.b_field().ty;
+        let c = op.c_field().ty;
+        writeln!(f, "pub type {camel_ident} = TernaryOp<{a}, {b}, {c}>;")
+    }
+}
+
 impl Display for DisplayDecode<&'_ CmpBranchOp> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         let op = self.value;

crates/ir2/build/display/encode.rs

@@ -12,6 +12,7 @@ use crate::build::{
         StoreOp,
         TableGetOp,
         TableSetOp,
+        TernaryOp,
         UnaryOp,
         V128LoadLaneOp,
         V128ReplaceLaneOp,
@@ -103,6 +104,7 @@ macro_rules! impl_display_encode {
 impl_display_encode! {
     UnaryOp,
     BinaryOp,
+    TernaryOp,
     CmpBranchOp,
     CmpSelectOp,
     LoadOp,

crates/ir2/build/display/ident.rs

@@ -11,6 +11,7 @@ use crate::build::{
         StoreOp,
         TableGetOp,
         TableSetOp,
+        TernaryOp,
         UnaryOp,
         V128LoadLaneOp,
         V128ReplaceLaneOp,
@@ -53,10 +54,9 @@ impl Display for DisplayIdent<&'_ UnaryOp> {
         let kind = op.kind;
         let ident = case.wrap(kind.ident());
         let sep = case.wrap(Sep);
-        let ident_prefix = DisplayConcat((case.wrap(kind.result_ty()), sep));
+        let ident_prefix = DisplayConcat((case.wrap(kind.ident_prefix()), sep));
         let ident_suffix = kind
-            .is_conversion()
-            .then_some(kind.value_ty())
+            .ident_suffix()
             .map(|i| (sep, case.wrap(i)))
             .map(DisplayConcat)
             .display_maybe();
@@ -86,6 +86,25 @@ impl Display for DisplayIdent<&'_ BinaryOp> {
     }
 }
 
+impl Display for DisplayIdent<&'_ TernaryOp> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        let case = self.case;
+        let sep = case.wrap(Sep);
+        let op = self.value;
+        let kind = op.kind;
+        let ident = case.wrap(kind.ident());
+        let ident_prefix = case.wrap(kind.ident_prefix());
+        let result_suffix = case.wrap(OperandKind::Slot);
+        let a_suffix = SnakeCase(OperandKind::Slot);
+        let b_suffix = SnakeCase(OperandKind::Slot);
+        let c_suffix = SnakeCase(OperandKind::Slot);
+        write!(
+            f,
+            "{ident_prefix}{sep}{ident}_{result_suffix}{a_suffix}{b_suffix}{c_suffix}"
+        )
+    }
+}
+
 impl Display for DisplayIdent<&'_ CmpBranchOp> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         let case = self.case;

crates/ir2/build/display/op.rs

@@ -15,6 +15,7 @@ use crate::build::{
         StoreOp,
         TableGetOp,
         TableSetOp,
+        TernaryOp,
         UnaryOp,
         V128LoadLaneOp,
         V128ReplaceLaneOp,
@@ -105,6 +106,7 @@ macro_rules! impl_display_variant {
 impl_display_variant! {
     UnaryOp,
     BinaryOp,
+    TernaryOp,
     CmpBranchOp,
     CmpSelectOp,
     LoadOp,

crates/ir2/build/display/result_mut.rs

@@ -10,6 +10,7 @@ use crate::build::{
         StoreOp,
         TableGetOp,
         TableSetOp,
+        TernaryOp,
         UnaryOp,
         V128LoadLaneOp,
         V128ReplaceLaneOp,
@@ -85,6 +86,12 @@ impl Display for DisplayResultMut<&'_ BinaryOp> {
     }
 }
 
+impl Display for DisplayResultMut<&'_ TernaryOp> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        self.display_match_arm(f)
+    }
+}
+
 impl Display for DisplayResultMut<&'_ CmpBranchOp> {
     fn fmt(&self, _f: &mut fmt::Formatter<'_>) -> fmt::Result {
         Ok(())

crates/ir2/build/ident.rs

@@ -306,8 +306,13 @@ define_ident!(
     Store32Lane: store32_lane,
     Store64Lane: store64_lane,
 
+    Bitselect: bitselect,
     RelaxedDotI8x16I7x16: relaxed_dot_i8x16_i7x16,
     RelaxedDotI8x16I7x16Add: relaxed_dot_i8x16_i7x16_add,
     RelaxedMadd: relaxed_madd,
     RelaxedNmadd: relaxed_nmadd,
+
+    A: a,
+    B: b,
+    C: c,
 );

crates/ir2/build/isa.rs

@@ -18,6 +18,8 @@ use crate::build::{
         StoreOpKind,
         TableGetOp,
         TableSetOp,
+        TernaryOp,
+        TernaryOpKind,
         Ty,
         UnaryOp,
         UnaryOpKind,
@@ -860,8 +862,6 @@ fn add_simd_binary_ops(isa: &mut Isa) {
         BinaryOpKind::U16x8Le,
         BinaryOpKind::U32x4Lt,
         BinaryOpKind::U32x4Le,
-        BinaryOpKind::U64x2Lt,
-        BinaryOpKind::U64x2Le,
         // Float Comparisons
         BinaryOpKind::F32x4Eq,
         BinaryOpKind::F32x4NotEq,
@@ -891,6 +891,7 @@ fn add_simd_binary_ops(isa: &mut Isa) {
         BinaryOpKind::U8x16Max,
         BinaryOpKind::U8x16Avgr,
         // i16x8 Ops
+        BinaryOpKind::S16x8RelaxedDotI8x16I7x16,
         BinaryOpKind::S16x8Q15MulrSat,
         BinaryOpKind::S16x8NarrowI32x4,
         BinaryOpKind::U16x8NarrowI32x4,
@@ -1115,14 +1116,14 @@ fn add_simd_store_ops(isa: &mut Isa) {
 
 fn add_relaxed_simd_ops(isa: &mut Isa) {
     let kinds = [
-        BinaryOpKind::S16x8RelaxedDotI8x16I7x16,
-        BinaryOpKind::S32x4RelaxedDotI8x16I7x16Add,
-        BinaryOpKind::F32x4RelaxedMadd,
-        BinaryOpKind::F32x4RelaxedNmadd,
-        BinaryOpKind::F64x2RelaxedMadd,
-        BinaryOpKind::F64x2RelaxedNmadd,
+        TernaryOpKind::I32x4RelaxedDotI8x16I7x16Add,
+        TernaryOpKind::F32x4RelaxedMadd,
+        TernaryOpKind::F32x4RelaxedNmadd,
+        TernaryOpKind::F64x2RelaxedMadd,
+        TernaryOpKind::F64x2RelaxedNmadd,
+        TernaryOpKind::V128Bitselect,
     ];
     for kind in kinds {
-        isa.push_op(BinaryOp::new(kind, OperandKind::Slot, OperandKind::Slot));
+        isa.push_op(TernaryOp::new(kind));
     }
 }