@@ -239,46 +239,6 @@ l610.upload.speed=460800
239
239
l610.upload.require_upload_port=false
240
240
l610.upload.wait_for_upload_port=false
241
241
242
- # s20gsm board definition
243
- s20gsm.name=S20 GSM Board
244
-
245
- # build
246
- s20gsm.build.core=logicrom
247
- s20gsm.build.cpu=arm9ejs
248
- s20gsm.build.f_cpu=260000000
249
- s20gsm.build.board=SIWI_S20GSM
250
- s20gsm.build.mcu=mt2503
251
- s20gsm.build.variant=s20u
252
- s20gsm.build.vid=0x0E8D
253
- s20gsm.build.pid=0x0003
254
- s20gsm.build.extra_flags=-DPLATFORM_S20U=1
255
- s20gsm.build.logicromlib=logicrom
256
- s20gsm.build.ldscript=linkerscript.ld
257
- s20gsm.menu.debug.Release=Release
258
- s20gsm.menu.debug.Release.build.build_type=
259
- s20gsm.menu.debug.Debug=Debug
260
- s20gsm.menu.debug.Debug.build.build_type=_debug
261
- s20gsm.menu.stdio.none=None
262
- s20gsm.menu.stdio.none.build.stdio_port=
263
- s20gsm.menu.stdio.ttys0=Uart0 (/dev/ttyS0)
264
- s20gsm.menu.stdio.ttys0.build.stdio_port=/dev/ttyS0
265
- s20gsm.menu.stdio.ttys1=Uart1 (/dev/ttyS1)
266
- s20gsm.menu.stdio.ttys1.build.stdio_port=/dev/ttyS1
267
- s20gsm.menu.stdio.ttys2=Uart2 (/dev/ttyS2)
268
- s20gsm.menu.stdio.ttys2.build.stdio_port=/dev/ttyS2
269
- s20gsm.menu.stdio.ttyusb=USB Uart (/dev/ttyUSB0)
270
- s20gsm.menu.stdio.ttyusb.build.stdio_port=/dev/ttyUSB0
271
-
272
- # upload
273
- s20gsm.bootloader.tool=logicromflasher
274
- s20gsm.upload.tool=logicromflasher
275
- s20gsm.upload.protocol=logicromflasher
276
- s20gsm.upload.maximum_size=262144
277
- s20gsm.upload.maximum_ram_size=96256
278
- s20gsm.upload.speed=460800
279
- s20gsm.upload.require_upload_port=true
280
- s20gsm.upload.wait_for_upload_port=true
281
-
282
242
# Quectel M66
283
243
quectelm66.name=Quectel M66
284
244
@@ -387,6 +347,46 @@ quectelmc20.upload.speed=460800
387
347
quectelmc20.upload.require_upload_port=true
388
348
quectelmc20.upload.wait_for_upload_port=true
389
349
350
+ # mc20u board definition
351
+ mc20u.name=Quectel MC20UCB
352
+
353
+ # build
354
+ mc20u.build.core=logicrom
355
+ mc20u.build.cpu=arm9ejs
356
+ mc20u.build.f_cpu=260000000
357
+ mc20u.build.board=SIWI_S20GSM
358
+ mc20u.build.mcu=mt2503
359
+ mc20u.build.variant=mc20u
360
+ mc20u.build.vid=0x0E8D
361
+ mc20u.build.pid=0x0003
362
+ mc20u.build.extra_flags=-DPLATFORM_MC20U=1
363
+ mc20u.build.logicromlib=logicrom
364
+ mc20u.build.ldscript=linkerscript.ld
365
+ mc20u.menu.debug.Release=Release
366
+ mc20u.menu.debug.Release.build.build_type=
367
+ mc20u.menu.debug.Debug=Debug
368
+ mc20u.menu.debug.Debug.build.build_type=_debug
369
+ mc20u.menu.stdio.none=None
370
+ mc20u.menu.stdio.none.build.stdio_port=
371
+ mc20u.menu.stdio.ttys0=Uart0 (/dev/ttyS0)
372
+ mc20u.menu.stdio.ttys0.build.stdio_port=/dev/ttyS0
373
+ mc20u.menu.stdio.ttys1=Uart1 (/dev/ttyS1)
374
+ mc20u.menu.stdio.ttys1.build.stdio_port=/dev/ttyS1
375
+ mc20u.menu.stdio.ttys2=Uart2 (/dev/ttyS2)
376
+ mc20u.menu.stdio.ttys2.build.stdio_port=/dev/ttyS2
377
+ mc20u.menu.stdio.ttyusb=USB Uart (/dev/ttyUSB0)
378
+ mc20u.menu.stdio.ttyusb.build.stdio_port=/dev/ttyUSB0
379
+
380
+ # upload
381
+ mc20u.bootloader.tool=logicromflasher
382
+ mc20u.upload.tool=logicromflasher
383
+ mc20u.upload.protocol=logicromflasher
384
+ mc20u.upload.maximum_size=262144
385
+ mc20u.upload.maximum_ram_size=96256
386
+ mc20u.upload.speed=460800
387
+ mc20u.upload.require_upload_port=true
388
+ mc20u.upload.wait_for_upload_port=true
389
+
390
390
# Quectel M56
391
391
quectelm56.name=Quectel M56
392
392
@@ -396,7 +396,7 @@ quectelm56.build.cpu=arm9ejs
396
396
quectelm56.build.f_cpu=260000000
397
397
quectelm56.build.board=QUECTEL_M56TEA
398
398
quectelm56.build.mcu=mt6261
399
- quectelm56.build.variant=s20u
399
+ quectelm56.build.variant=mc20u
400
400
quectelm56.build.extra_flags=-DPLATFORM_M56=1
401
401
quectelm56.build.logicromlib=logicrom
402
402
quectelm56.build.ldscript=linkerscript.ld
0 commit comments