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1 |
| -#ifndef INCLUDE_PLAT_DEF_ADC_H_ |
2 |
| -#define INCLUDE_PLAT_DEF_ADC_H_ |
3 |
| - |
4 |
| -/** |
5 |
| - * ADC channels |
6 |
| - */ |
7 |
| -enum adcch_e |
8 |
| -{ |
9 |
| -#if defined(PLATFORM_M56) || defined(_DOXYGEN_) |
10 |
| - ADC_CH0, /**< ADC channel 0 - Pin 61 */ |
11 |
| - ADC_CH1, /**< ADC channel 1 - Pin 12 */ |
12 |
| - ADC_CH2, /**< ADC channel 2 - Pin 3 */ |
13 |
| - ADC_CH3, /**< ADC channel 3 - Pin 2 */ |
14 |
| - ADC_CH4, /**< ADC channel 4 - Pin 13 */ |
15 |
| - ADC_CH5, /**< ADC channel 5 - Pin 33 */ |
16 |
| -#elif defined(PLATFORM_S20U) |
17 |
| - ADC_CH0, /**< ADC channel 0 - Pin 6 */ |
18 |
| - ADC_CH1, /**< ADC channel 1 - Pin 47 */ |
19 |
| - ADC_CH2, /**< ADC channel 2 - Pin 66 */ |
20 |
| - ADC_CH3, /**< ADC channel 3 - Pin 30 */ |
21 |
| - ADC_CH4, /**< ADC channel 4 - Pin 29 */ |
22 |
| -#elif defined(PLATFORM_BC20) |
23 |
| - ADC_CH0, /**< ADC channel 0 - Pin 6 */ |
24 |
| - ADC_CH1, /**< ADC channel 1 - Pin 54 */ |
25 |
| -#elif defined(PLATFORM_SIM868) |
26 |
| - ADC_CH0, /**< ADC channel 0 - Pin 38 */ |
27 |
| -#elif defined(PLATFORM_M66) |
28 |
| - ADC_CH0, /**< ADC channel 0 - Pin 9 */ |
29 |
| - ADC_CH1, /**< ADC channel 1 - Pin 16 */ |
30 |
| - ADC_CH2, /**< ADC channel 2 - Pin 28 */ |
31 |
| - ADC_CH3, /**< ADC channel 3 - Pin 29 */ |
32 |
| -#else |
33 |
| - ADC_CH0, /**< ADC channel 0 - Pin 6 */ |
34 |
| - ADC_CH1, /**< ADC channel 1 - Pin 47 */ |
35 |
| - ADC_CH2, /**< ADC channel 2 - Pin 28 */ |
36 |
| - ADC_CH3, /**< ADC channel 3 - Pin 29 */ |
37 |
| -#endif |
38 |
| -}; |
39 |
| - |
40 |
| -#endif /* INCLUDE_PLAT_DEF_ADC_H_ */ |
| 1 | +#ifndef INCLUDE_PLAT_DEF_ADC_H_ |
| 2 | +#define INCLUDE_PLAT_DEF_ADC_H_ |
| 3 | + |
| 4 | +/** |
| 5 | + * ADC channels |
| 6 | + */ |
| 7 | +enum adcch_e |
| 8 | +{ |
| 9 | +#if defined(PLATFORM_M56) || defined(_DOXYGEN_) |
| 10 | + ADC_CH0, /**< ADC channel 0 - Pin 61 */ |
| 11 | + ADC_CH1, /**< ADC channel 1 - Pin 12 */ |
| 12 | + ADC_CH2, /**< ADC channel 2 - Pin 3 */ |
| 13 | + ADC_CH3, /**< ADC channel 3 - Pin 2 */ |
| 14 | + ADC_CH4, /**< ADC channel 4 - Pin 13 */ |
| 15 | + ADC_CH5, /**< ADC channel 5 - Pin 33 */ |
| 16 | +#elif defined(PLATFORM_S20U) |
| 17 | + ADC_CH0, /**< ADC channel 0 - Pin 6 */ |
| 18 | + ADC_CH1, /**< ADC channel 1 - Pin 47 */ |
| 19 | + ADC_CH2, /**< ADC channel 2 - Pin 66 */ |
| 20 | + ADC_CH3, /**< ADC channel 3 - Pin 30 */ |
| 21 | + ADC_CH4, /**< ADC channel 4 - Pin 29 */ |
| 22 | +#elif defined(PLATFORM_BC20) |
| 23 | + ADC_CH0, /**< ADC channel 0 - Pin 6 */ |
| 24 | + ADC_CH1, /**< ADC channel 1 - Pin 54 */ |
| 25 | +#elif defined(PLATFORM_SIM868) |
| 26 | + ADC_CH0, /**< ADC channel 0 - Pin 38 */ |
| 27 | +#elif defined(PLATFORM_M66) |
| 28 | + ADC_CH0, /**< ADC channel 0 - Pin 9 */ |
| 29 | + ADC_CH1, /**< ADC channel 1 - Pin 16 */ |
| 30 | + ADC_CH2, /**< ADC channel 2 - Pin 28 */ |
| 31 | + ADC_CH3, /**< ADC channel 3 - Pin 29 */ |
| 32 | +#else |
| 33 | + ADC_CH0, /**< ADC channel 0 - Pin 6 */ |
| 34 | + ADC_CH1, /**< ADC channel 1 - Pin 47 */ |
| 35 | + ADC_CH2, /**< ADC channel 2 - Pin 28 */ |
| 36 | + ADC_CH3, /**< ADC channel 3 - Pin 29 */ |
| 37 | +#endif |
| 38 | +}; |
| 39 | + |
| 40 | +#endif /* INCLUDE_PLAT_DEF_ADC_H_ */ |
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