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ajaybhargavajaybhargav
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boards:update ASR160x module files
Signed-off-by: Ajay Bhargav <[email protected]>
1 parent 127871b commit db24049

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10 files changed

+30
-20
lines changed

10 files changed

+30
-20
lines changed

‎boards/a7670.json‎

Lines changed: 3 additions & 2 deletions
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{
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"build": {
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"core": "logicrom",
4-
"cpu": "armv7a",
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"cpu": "armv7r",
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"f_cpu": "416000000L",
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"mcu": "ASR1601",
7-
"variant": "a7670",
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"variant": "asr160x",
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"flashsz": "16M",
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"logicromtype": "release",
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"extra_flags": "-DSOC_ASR160X=1 -DSOC_ASR1601=1 -DPLATFORM_A7670=1",
@@ -20,6 +20,7 @@
2020
"LTE Cat.1"
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],
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"frameworks": [
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"arduino",
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"logicromsdk"
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],
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"name": "SIMCOM A7670X LTE Cat.1 Module",

‎boards/ec100n.json‎

Lines changed: 3 additions & 2 deletions
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{
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"build": {
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"core": "logicrom",
4-
"cpu": "armv7a",
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"cpu": "armv7r",
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"f_cpu": "416000000L",
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"mcu": "ASR1603",
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"variant": "ec100n",
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"variant": "asr160x",
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"flashsz": "16M",
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"logicromtype": "release",
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"extra_flags": "-DSOC_ASR160X=1 -DSOC_ASR1603=1 -DPLATFORM_EC100N=1",
@@ -20,6 +20,7 @@
2020
"LTE Cat.1"
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],
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"frameworks": [
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"arduino",
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"logicromsdk"
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],
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"name": "Quectel EC100N LTE Cat.1 Module",

‎boards/ec100s.json‎

Lines changed: 3 additions & 2 deletions
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{
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"build": {
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"core": "logicrom",
4-
"cpu": "armv7a",
4+
"cpu": "armv7r",
55
"f_cpu": "416000000L",
66
"mcu": "ASR1601",
7-
"variant": "ec100s",
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"variant": "asr160x",
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"flashsz": "16M",
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"logicromtype": "release",
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"extra_flags": "-DSOC_ASR160X=1 -DSOC_ASR1601=1 -DPLATFORM_EC100S=1",
@@ -20,6 +20,7 @@
2020
"LTE Cat.1"
2121
],
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"frameworks": [
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"arduino",
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"logicromsdk"
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],
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"name": "Quectel EC100S LTE Cat.1 Module",

‎boards/ec100y.json‎

Lines changed: 3 additions & 2 deletions
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{
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"build": {
33
"core": "logicrom",
4-
"cpu": "armv7a",
4+
"cpu": "armv7r",
55
"f_cpu": "416000000L",
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"mcu": "ASR1601",
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"variant": "ec100y",
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"variant": "asr160x",
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"flashsz": "16M",
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"logicromtype": "release",
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"extra_flags": "-DSOC_ASR160X=1 -DSOC_ASR1601=1 -DPLATFORM_EC100Y=1",
@@ -20,6 +20,7 @@
2020
"LTE Cat.1"
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],
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"frameworks": [
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"arduino",
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"logicromsdk"
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],
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"name": "Quectel EC100Y LTE Cat.1 Module",

‎boards/ec200n.json‎

Lines changed: 3 additions & 2 deletions
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{
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"build": {
33
"core": "logicrom",
4-
"cpu": "armv7a",
4+
"cpu": "armv7r",
55
"f_cpu": "416000000L",
66
"mcu": "ASR1603",
7-
"variant": "ec200n",
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"variant": "asr160x",
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"flashsz": "8M",
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"logicromtype": "release",
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"extra_flags": "-DSOC_ASR160X=1 -DSOC_ASR1603=1 -DPLATFORM_EC200N=1",
@@ -20,6 +20,7 @@
2020
"LTE Cat.1"
2121
],
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"frameworks": [
23+
"arduino",
2324
"logicromsdk"
2425
],
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"name": "Quectel EC200N LTE Cat.1 Module",

‎boards/ec200s.json‎

Lines changed: 3 additions & 2 deletions
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{
22
"build": {
33
"core": "logicrom",
4-
"cpu": "armv7a",
4+
"cpu": "armv7r",
55
"f_cpu": "416000000L",
66
"mcu": "ASR1601",
7-
"variant": "ec200s",
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"variant": "asr160x",
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"flashsz": "16M",
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"logicromtype": "release",
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"extra_flags": "-DSOC_ASR160X=1 -DSOC_ASR1601=1 -DPLATFORM_EC200S=1",
@@ -20,6 +20,7 @@
2020
"LTE Cat.1"
2121
],
2222
"frameworks": [
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"arduino",
2324
"logicromsdk"
2425
],
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"name": "Quectel EC200S LTE Cat.1 Module",

‎boards/ec600n.json‎

Lines changed: 3 additions & 2 deletions
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{
22
"build": {
33
"core": "logicrom",
4-
"cpu": "armv7a",
4+
"cpu": "armv7r",
55
"f_cpu": "416000000L",
66
"mcu": "ASR1603",
7-
"variant": "ec600n",
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"variant": "asr160x",
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"flashsz": "16M",
99
"logicromtype": "release",
1010
"extra_flags": "-DSOC_ASR160X=1 -DSOC_ASR1603=1 -DPLATFORM_EC600N=1",
@@ -20,6 +20,7 @@
2020
"LTE Cat.1"
2121
],
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"frameworks": [
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"arduino",
2324
"logicromsdk"
2425
],
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"name": "Quectel EC600N LTE Cat.1 Module",

‎boards/ec600s.json‎

Lines changed: 3 additions & 2 deletions
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{
22
"build": {
33
"core": "logicrom",
4-
"cpu": "armv7a",
4+
"cpu": "armv7r",
55
"f_cpu": "416000000L",
66
"mcu": "ASR1601",
7-
"variant": "ec100s",
7+
"variant": "asr160x",
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"flashsz": "16M",
99
"logicromtype": "release",
1010
"extra_flags": "-DSOC_ASR160X=1 -DSOC_ASR1601=1 -DPLATFORM_EC600S=1",
@@ -20,6 +20,7 @@
2020
"LTE Cat.1"
2121
],
2222
"frameworks": [
23+
"arduino",
2324
"logicromsdk"
2425
],
2526
"name": "Quectel EC600S LTE Cat.1 Module",

‎boards/eg912y.json‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
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{
22
"build": {
33
"core": "logicrom",
4-
"cpu": "armv7a",
4+
"cpu": "armv7r",
55
"f_cpu": "416000000L",
66
"mcu": "ASR1603",
7-
"variant": "eg912y",
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"variant": "asr160x",
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"flashsz": "8M",
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"logicromtype": "release",
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"extra_flags": "-DSOC_ASR160X=1 -DSOC_ASR1603=1 -DPLATFORM_EG912Y=1",
@@ -20,6 +20,7 @@
2020
"LTE Cat.1"
2121
],
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"frameworks": [
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"arduino",
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"logicromsdk"
2425
],
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"name": "Quectel EG912Y LTE Cat.1 Module",

‎boards/eg915n.json‎

Lines changed: 3 additions & 2 deletions
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{
22
"build": {
33
"core": "logicrom",
4-
"cpu": "armv7a",
4+
"cpu": "armv7r",
55
"f_cpu": "416000000L",
66
"mcu": "ASR1603",
7-
"variant": "eg915n",
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"variant": "asr160x",
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"flashsz": "16M",
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"logicromtype": "release",
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"extra_flags": "-DSOC_ASR160X=1 -DSOC_ASR1603=1 -DPLATFORM_EG915N=1",
@@ -20,6 +20,7 @@
2020
"LTE Cat.1"
2121
],
2222
"frameworks": [
23+
"arduino",
2324
"logicromsdk"
2425
],
2526
"name": "Quectel EG915N LTE Cat.1 Module",

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