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[DT][NFC] Trim unnecessary IRs for materialize_encoding_vmvx.mlir test. (iree-org#22330)
It is a step towards iree-org#20825 Signed-off-by: hanhanW <[email protected]> Signed-off-by: Philipp <[email protected]>
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‎compiler/src/iree/compiler/Codegen/Common/test/materialize_encoding_vmvx.mlir‎

Lines changed: 40 additions & 158 deletions
Original file line numberDiff line numberDiff line change
@@ -31,223 +31,105 @@ func.func @matmul_lowering_i8i8i32_vmvx_ukernel(
3131

3232
// -----
3333

34-
#pipeline_layout = #hal.pipeline.layout<bindings = [
35-
#hal.pipeline.binding<storage_buffer>,
36-
#hal.pipeline.binding<storage_buffer>,
37-
#hal.pipeline.binding<storage_buffer>
38-
]>
39-
#map = affine_map<()[s0] -> ((3 ceildiv s0) * s0)>
40-
#map1 = affine_map<()[s0] -> ((1 ceildiv s0) * s0)>
4134
#map2 = affine_map<(d0, d1, d2) -> (d0, d2)>
4235
#map3 = affine_map<(d0, d1, d2) -> (d2, d1)>
4336
#map4 = affine_map<(d0, d1, d2) -> (d0, d1)>
4437
#encoding_lhs = #iree_encoding.encoding<operand_index = 0, op_type = matmul, element_types = [f32, f32, f32], user_indexing_maps = [#map2, #map3, #map4], iteration_sizes = [1, 3, 2]>
4538
#encoding_rhs = #iree_encoding.encoding<operand_index = 1, op_type = matmul, element_types = [f32, f32, f32], user_indexing_maps = [#map2, #map3, #map4], iteration_sizes = [1, 3, 2]>
4639
#encoding_result = #iree_encoding.encoding<operand_index = 2, op_type = matmul, element_types = [f32, f32, f32], user_indexing_maps = [#map2, #map3, #map4], iteration_sizes = [1, 3, 2]>
47-
func.func @fill_matmul() attributes {
40+
func.func @fill_matmul(
41+
%lhs: tensor<1x2xf32, #encoding_lhs>,
42+
%rhs: tensor<2x3xf32, #encoding_rhs>
43+
) -> tensor<1x3xf32, #encoding_result> attributes {
4844
hal.executable.target = #hal.executable.target<"vmvx", "vmvx-bytecode-fb", {iree.encoding.resolver = #iree_cpu.vmvx_encoding_resolver<>}>
4945
} {
50-
%c32_i64 = arith.constant 32 : i64
5146
%cst = arith.constant 0.000000e+00 : f32
52-
%c0 = arith.constant 0 : index
53-
%0 = hal.interface.binding.subspan layout(#pipeline_layout) binding(0) alignment(64) offset(%c0) flags(ReadOnly) : !iree_tensor_ext.dispatch.tensor<readonly:tensor<1x2xf32, #encoding_lhs>>
54-
%1 = hal.interface.binding.subspan layout(#pipeline_layout) binding(1) alignment(64) offset(%c0) flags(ReadOnly) : !iree_tensor_ext.dispatch.tensor<readonly:tensor<2x3xf32, #encoding_rhs>>
55-
%2 = hal.interface.binding.subspan layout(#pipeline_layout) binding(2) alignment(64) offset(%c0) : !iree_tensor_ext.dispatch.tensor<writeonly:tensor<1x3xf32, #encoding_result>>
56-
%3 = iree_tensor_ext.dispatch.tensor.load %0, offsets = [0, 0], sizes = [1, 2], strides = [1, 1] : !iree_tensor_ext.dispatch.tensor<readonly:tensor<1x2xf32, #encoding_lhs>> -> tensor<1x2xf32, #encoding_lhs>
57-
%4 = iree_tensor_ext.dispatch.tensor.load %1, offsets = [0, 0], sizes = [2, 3], strides = [1, 1] : !iree_tensor_ext.dispatch.tensor<readonly:tensor<2x3xf32, #encoding_rhs>> -> tensor<2x3xf32, #encoding_rhs>
58-
%7 = tensor.empty() : tensor<1x3xf32, #encoding_result>
59-
%8 = linalg.fill ins(%cst : f32) outs(%7 : tensor<1x3xf32, #encoding_result>) -> tensor<1x3xf32, #encoding_result>
60-
%9 = linalg.matmul ins(%3, %4 : tensor<1x2xf32, #encoding_lhs>, tensor<2x3xf32, #encoding_rhs>) outs(%8 : tensor<1x3xf32, #encoding_result>) -> tensor<1x3xf32, #encoding_result>
61-
iree_tensor_ext.dispatch.tensor.store %9, %2, offsets = [0, 0], sizes = [1, 3], strides = [1, 1] : tensor<1x3xf32, #encoding_result> -> !iree_tensor_ext.dispatch.tensor<writeonly:tensor<1x3xf32, #encoding_result>>
62-
return
47+
%empty = tensor.empty() : tensor<1x3xf32, #encoding_result>
48+
%filled = linalg.fill ins(%cst : f32) outs(%empty : tensor<1x3xf32, #encoding_result>) -> tensor<1x3xf32, #encoding_result>
49+
%result = linalg.matmul ins(%lhs, %rhs : tensor<1x2xf32, #encoding_lhs>, tensor<2x3xf32, #encoding_rhs>) outs(%filled : tensor<1x3xf32, #encoding_result>) -> tensor<1x3xf32, #encoding_result>
50+
return %result : tensor<1x3xf32, #encoding_result>
6351
}
6452
// CHECK: func.func @fill_matmul
53+
// CHECK-SAME: %[[LHS:.+]]: tensor<1x1x1x4xf32>
54+
// CHECK-SAME: %[[RHS:.+]]: tensor<1x1x8x4xf32>
6555
// CHECK-DAG: %[[ZERO:.+]] = arith.constant 0.000000e+00 : f32
66-
// CHECK: %[[LHS_BINDING:.+]] = hal.interface.binding.subspan layout({{.+}}) binding(0)
67-
// CHECK-SAME: !iree_tensor_ext.dispatch.tensor<readonly:tensor<1x1x1x4xf32>>
68-
// CHECK: %[[RHS_BINDING:.+]] = hal.interface.binding.subspan layout({{.+}}) binding(1)
69-
// CHECK-SAME: !iree_tensor_ext.dispatch.tensor<readonly:tensor<1x1x8x4xf32>>
70-
// CHECK: %[[OUTS_BINDING:.+]] = hal.interface.binding.subspan layout({{.+}}) binding(2)
71-
// CHECK-SAME: !iree_tensor_ext.dispatch.tensor<writeonly:tensor<1x1x1x8xf32>>
72-
// CHECK: %[[LHS:.+]] = iree_tensor_ext.dispatch.tensor.load %[[LHS_BINDING]]
73-
// CHECK-SAME: offsets = [0, 0, 0, 0], sizes = [1, 1, 1, 4], strides = [1, 1, 1, 1]
74-
// CHECK: %[[RHS:.+]] = iree_tensor_ext.dispatch.tensor.load %[[RHS_BINDING]]
75-
// CHECK-SAME: offsets = [0, 0, 0, 0], sizes = [1, 1, 8, 4], strides = [1, 1, 1, 1]
7656
// CHECK: %[[EMPTY:.+]] = tensor.empty() : tensor<1x1x1x8xf32>
7757
// CHECK: %[[FILL:.+]] = linalg.fill
7858
// CHECK-SAME: ins(%[[ZERO]]
7959
// CHECK-SAME: outs(%[[EMPTY]]
80-
// CHECK: %[[MMT4D:.+]] = linalg.mmt4d
60+
// CHECK: %[[MATMUL:.+]] = linalg.mmt4d
8161
// CHECK-SAME: ins(%[[LHS]], %[[RHS]]
8262
// CHECK-SAME: outs(%[[FILL]]
83-
// CHECK: iree_tensor_ext.dispatch.tensor.store %[[MMT4D]], %[[OUTS_BINDING]]
84-
// CHECK-SAME: offsets = [0, 0, 0, 0], sizes = [1, 1, 1, 8], strides = [1, 1, 1, 1]
63+
// CHECK: return %[[MATMUL]]
8564

8665
// -----
8766

88-
#pipeline_layout = #hal.pipeline.layout<constants = 2, bindings = [
89-
#hal.pipeline.binding<storage_buffer>,
90-
#hal.pipeline.binding<storage_buffer>
91-
]>
9267
#map = affine_map<(d0, d1, d2) -> (d0, d2)>
9368
#map1 = affine_map<(d0, d1, d2) -> (d2, d1)>
9469
#map2 = affine_map<(d0, d1, d2) -> (d0, d1)>
9570
#encoding_lhs = #iree_encoding.encoding<operand_index = 0, op_type = matmul, element_types = [f32, f32, f32], user_indexing_maps = [#map, #map1, #map2], iteration_sizes = [?, ?, ?]>
96-
func.func @set_encoding_dynamic() attributes {
71+
func.func @set_encoding_dynamic(%input: tensor<?x?xf32>) -> tensor<?x?xf32, #encoding_lhs> attributes {
9772
hal.executable.target = #hal.executable.target<"vmvx", "vmvx-bytecode-fb", {iree.encoding.resolver = #iree_cpu.vmvx_encoding_resolver<>}>
9873
} {
99-
%c0 = arith.constant 0 : index
100-
%d0 = hal.interface.constant.load layout(#pipeline_layout) ordinal(0) : index
101-
%d1 = hal.interface.constant.load layout(#pipeline_layout) ordinal(1) : index
102-
%0 = hal.interface.binding.subspan layout(#pipeline_layout) binding(0) alignment(64) offset(%c0)
103-
: !iree_tensor_ext.dispatch.tensor<readonly:tensor<?x?xf32>>{%d0, %d1}
104-
%1 = hal.interface.binding.subspan layout(#pipeline_layout) binding(1) alignment(64) offset(%c0)
105-
: !iree_tensor_ext.dispatch.tensor<writeonly:tensor<?x?xf32, #encoding_lhs>>{%d0, %d1}
106-
%2 = iree_tensor_ext.dispatch.tensor.load %0, offsets = [0, 0], sizes = [%d0, %d1], strides = [1, 1]
107-
: !iree_tensor_ext.dispatch.tensor<readonly:tensor<?x?xf32>>{%d0, %d1} -> tensor<?x?xf32>
108-
%3 = iree_encoding.set_encoding %2 : tensor<?x?xf32> -> tensor<?x?xf32, #encoding_lhs>
109-
iree_tensor_ext.dispatch.tensor.store %3, %1, offsets = [0, 0], sizes = [%d0, %d1], strides = [1, 1]
110-
: tensor<?x?xf32, #encoding_lhs>
111-
-> !iree_tensor_ext.dispatch.tensor<writeonly:tensor<?x?xf32, #encoding_lhs>>{%d0, %d1}
112-
return
74+
%0 = iree_encoding.set_encoding %input : tensor<?x?xf32> -> tensor<?x?xf32, #encoding_lhs>
75+
return %0 : tensor<?x?xf32, #encoding_lhs>
11376
}
11477
// CHECK-DAG: #[[MAP0:.+]] = affine_map<()[s0] -> (s0 ceildiv 8)>
11578
// CHECK-DAG: #[[MAP1:.+]] = affine_map<()[s0] -> (s0 ceildiv 4)>
116-
// CHECK: func @set_encoding_dynamic()
117-
// CHECK-DAG: %[[C0:.+]] = arith.constant 0 : index
118-
// CHECK-DAG: %[[CST:.+]] = arith.constant 0.0
119-
// CHECK-DAG: %[[D0:.+]] = hal.interface.constant.load layout({{.+}}) ordinal(0)
120-
// CHECK-DAG: %[[D1:.+]] = hal.interface.constant.load layout({{.+}}) ordinal(1)
121-
// CHECK: %[[INPUT_BINDING:.+]] = hal.interface.binding.subspan layout({{.+}}) binding(0)
122-
// CHECK-DAG: %[[TILED_D0:.+]] = affine.apply #[[MAP0]]()[%[[D0]]]
123-
// CHECK-DAG: %[[TILED_D1:.+]] = affine.apply #[[MAP1]]()[%[[D1]]]
124-
// CHECK-DAG: %[[OUTPUT_BINDING:.+]] = hal.interface.binding.subspan layout({{.+}}) binding(1)
125-
// CHECK-SAME: !iree_tensor_ext.dispatch.tensor<writeonly:tensor<?x?x8x4xf32>>{%[[TILED_D0]], %[[TILED_D1]]}
126-
// CHECK: %[[INPUT:.+]] = iree_tensor_ext.dispatch.tensor.load %[[INPUT_BINDING]]
79+
// CHECK: func @set_encoding_dynamic(
80+
// CHECK-SAME: %[[INPUT:[a-zA-Z0-9]+]]: tensor<?x?xf32>
81+
// CHECK: %[[CST:.+]] = arith.constant 0.000000e+00 : f32
12782
// CHECK: %[[EMPTY:.+]] = tensor.empty
12883
// CHECK: %[[PACK:.+]] = linalg.pack
12984
// CHECK-SAME: %[[INPUT]] padding_value(%[[CST]] : f32)
13085
// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [8, 4] into %[[EMPTY]]
131-
// CHECK: iree_tensor_ext.dispatch.tensor.store %[[PACK]], %[[OUTPUT_BINDING]]
132-
// CHECK-SAME: offsets = [0, 0, 0, 0], sizes = [%[[TILED_D0]], %[[TILED_D1]], 8, 4], strides = [1, 1, 1, 1]
86+
// CHECK: return %[[PACK]]
13387

13488
// -----
13589

136-
#pipeline_layout = #hal.pipeline.layout<constants = 2, bindings = [
137-
#hal.pipeline.binding<storage_buffer>,
138-
#hal.pipeline.binding<storage_buffer>
139-
]>
14090
#map = affine_map<(d0, d1, d2) -> (d0, d2)>
14191
#map1 = affine_map<(d0, d1, d2) -> (d2, d1)>
14292
#map2 = affine_map<(d0, d1, d2) -> (d0, d1)>
14393
#encoding_lhs = #iree_encoding.encoding<operand_index = 0, op_type = matmul, element_types = [f32, f32, f32], user_indexing_maps = [#map, #map1, #map2], iteration_sizes = [?, ?, ?]>
144-
func.func @unset_encoding_dynamic() attributes {
94+
func.func @unset_encoding_dynamic(%input: tensor<?x?xf32, #encoding_lhs>, %d0: index, %d1: index) -> tensor<?x?xf32> attributes {
14595
hal.executable.target = #hal.executable.target<"vmvx", "vmvx-bytecode-fb", {iree.encoding.resolver = #iree_cpu.vmvx_encoding_resolver<>}>
14696
} {
147-
%c0 = arith.constant 0 : index
148-
%cst = arith.constant 0.000000e+00 : f32
149-
%d0 = hal.interface.constant.load layout(#pipeline_layout) ordinal(0) : index
150-
%d1 = hal.interface.constant.load layout(#pipeline_layout) ordinal(1) : index
151-
%0 = hal.interface.binding.subspan layout(#pipeline_layout) binding(0) alignment(64) offset(%c0)
152-
: !iree_tensor_ext.dispatch.tensor<readonly:tensor<?x?xf32, #encoding_lhs>>{%d0, %d1}
153-
%1 = hal.interface.binding.subspan layout(#pipeline_layout) binding(1) alignment(64) offset(%c0)
154-
: !iree_tensor_ext.dispatch.tensor<writeonly:tensor<?x?xf32>>{%d0, %d1}
155-
%2 = iree_tensor_ext.dispatch.tensor.load %0, offsets = [0, 0], sizes = [%d0, %d1], strides = [1, 1]
156-
: !iree_tensor_ext.dispatch.tensor<readonly:tensor<?x?xf32, #encoding_lhs>>{%d0, %d1}
157-
-> tensor<?x?xf32, #encoding_lhs>
158-
%3 = iree_encoding.unset_encoding %2
159-
: tensor<?x?xf32, #encoding_lhs> -> tensor<?x?xf32>{%d0, %d1}
160-
iree_tensor_ext.dispatch.tensor.store %3, %1, offsets = [0, 0], sizes = [%d0, %d1], strides = [1, 1]
161-
: tensor<?x?xf32> -> !iree_tensor_ext.dispatch.tensor<writeonly:tensor<?x?xf32>>{%d0, %d1}
162-
return
97+
%0 = iree_encoding.unset_encoding %input : tensor<?x?xf32, #encoding_lhs> -> tensor<?x?xf32>{%d0, %d1}
98+
return %0 : tensor<?x?xf32>
16399
}
164-
// CHECK-DAG: #[[MAP0:.+]] = affine_map<()[s0] -> (s0 ceildiv 8)>
165-
// CHECK-DAG: #[[MAP1:.+]] = affine_map<()[s0] -> (s0 ceildiv 4)>
166-
// CHECK: func @unset_encoding_dynamic()
167-
// CHECK-DAG: %[[C0:.+]] = arith.constant 0 : index
168-
// CHECK-DAG: %[[D0:.+]] = hal.interface.constant.load layout({{.+}}) ordinal(0)
169-
// CHECK-DAG: %[[D1:.+]] = hal.interface.constant.load layout({{.+}}) ordinal(1)
170-
// CHECK-DAG: %[[TILED_D0:.+]] = affine.apply #[[MAP0]]()[%[[D0]]]
171-
// CHECK-DAG: %[[TILED_D1:.+]] = affine.apply #[[MAP1]]()[%[[D1]]]
172-
// CHECK-DAG: %[[INPUT_BINDING:.+]] = hal.interface.binding.subspan layout({{.+}}) binding(0)
173-
// CHECK-SAME: !iree_tensor_ext.dispatch.tensor<readonly:tensor<?x?x8x4xf32>>{%[[TILED_D0]], %[[TILED_D1]]}
174-
// CHECK-DAG: %[[OUTPUT_BINDING:.+]] = hal.interface.binding.subspan layout({{.+}}) binding(1)
175-
// CHECK: %[[INPUT:.+]] = iree_tensor_ext.dispatch.tensor.load %[[INPUT_BINDING]]
176-
// CHECK-SAME: offsets = [0, 0, 0, 0], sizes = [%[[TILED_D0]], %[[TILED_D1]], 8, 4], strides = [1, 1, 1, 1]
177-
// CHECK: %[[EMPTY:.+]] = tensor.empty(%[[D0]], %[[D1]])
100+
// CHECK: func @unset_encoding_dynamic(
101+
// CHECK-SAME: %[[INPUT:[a-zA-Z0-9]+]]: tensor<?x?x8x4xf32>
102+
// CHECK: %[[EMPTY:.+]] = tensor.empty
178103
// CHECK: %[[UNPACK:.+]] = linalg.unpack %[[INPUT]]
179104
// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [8, 4] into %[[EMPTY]]
180-
// CHECK-DAG: iree_tensor_ext.dispatch.tensor.store %[[UNPACK]], %[[OUTPUT_BINDING]]
105+
// CHECK: return %[[UNPACK]]
181106

182107
// -----
183108

184-
#pipeline_layout = #hal.pipeline.layout<constants = 3, bindings = [
185-
#hal.pipeline.binding<storage_buffer>,
186-
#hal.pipeline.binding<storage_buffer>,
187-
#hal.pipeline.binding<storage_buffer>
188-
]>
189109
#map = affine_map<(d0, d1, d2) -> (d0, d2)>
190110
#map1 = affine_map<(d0, d1, d2) -> (d2, d1)>
191111
#map2 = affine_map<(d0, d1, d2) -> (d0, d1)>
192112
#encoding_lhs = #iree_encoding.encoding<operand_index = 0, op_type = matmul, element_types = [f32, f32, f32], user_indexing_maps = [#map, #map1, #map2], iteration_sizes = [?, ?, ?]>
193113
#encoding_rhs = #iree_encoding.encoding<operand_index = 1, op_type = matmul, element_types = [f32, f32, f32], user_indexing_maps = [#map, #map1, #map2], iteration_sizes = [?, ?, ?]>
194114
#encoding_result = #iree_encoding.encoding<operand_index = 2, op_type = matmul, element_types = [f32, f32, f32], user_indexing_maps = [#map, #map1, #map2], iteration_sizes = [?, ?, ?]>
195-
func.func @matmul_lowering_f32f32f32_generic() attributes {
115+
func.func @matmul_lowering_f32f32f32_generic(
116+
%lhs: tensor<?x?xf32, #encoding_lhs>,
117+
%rhs: tensor<?x?xf32, #encoding_rhs>,
118+
%result: tensor<?x?xf32, #encoding_result>
119+
) -> tensor<?x?xf32, #encoding_result> attributes {
196120
hal.executable.target = #hal.executable.target<"vmvx", "vmvx-bytecode-fb", {iree.encoding.resolver = #iree_cpu.vmvx_encoding_resolver<>}>
197121
} {
198-
%c0 = arith.constant 0 : index
199-
%M = hal.interface.constant.load layout(#pipeline_layout) ordinal(0) : index
200-
%N = hal.interface.constant.load layout(#pipeline_layout) ordinal(1) : index
201-
%K = hal.interface.constant.load layout(#pipeline_layout) ordinal(2) : index
202-
%0 = hal.interface.binding.subspan layout(#pipeline_layout) binding(0) alignment(64) offset(%c0)
203-
: !iree_tensor_ext.dispatch.tensor<readonly:tensor<?x?xf32, #encoding_lhs>>{%M, %K}
204-
%1 = hal.interface.binding.subspan layout(#pipeline_layout) binding(1) alignment(64) offset(%c0)
205-
: !iree_tensor_ext.dispatch.tensor<readonly:tensor<?x?xf32, #encoding_rhs>>{%K, %N}
206-
%2 = hal.interface.binding.subspan layout(#pipeline_layout) binding(2) alignment(64) offset(%c0)
207-
: !iree_tensor_ext.dispatch.tensor<readwrite:tensor<?x?xf32, #encoding_result>>{%M, %N}
208-
%3 = iree_tensor_ext.dispatch.tensor.load %0, offsets = [0, 0], sizes = [%M, %K], strides = [1, 1]
209-
: !iree_tensor_ext.dispatch.tensor<readonly:tensor<?x?xf32, #encoding_lhs>>{%M, %K}
210-
-> tensor<?x?xf32, #encoding_lhs>
211-
%4 = iree_tensor_ext.dispatch.tensor.load %1, offsets = [0, 0], sizes = [%K, %N], strides = [1, 1]
212-
: !iree_tensor_ext.dispatch.tensor<readonly:tensor<?x?xf32, #encoding_rhs>>{%K, %N}
213-
-> tensor<?x?xf32, #encoding_rhs>
214-
%5 = iree_tensor_ext.dispatch.tensor.load %2, offsets = [0, 0], sizes = [%M, %N], strides = [1, 1]
215-
: !iree_tensor_ext.dispatch.tensor<readwrite:tensor<?x?xf32, #encoding_result>>{%M, %N}
216-
-> tensor<?x?xf32, #encoding_result>
217-
%6 = linalg.matmul
218-
ins(%3, %4 : tensor<?x?xf32, #encoding_lhs>,
219-
tensor<?x?xf32, #encoding_rhs>)
220-
outs(%5 : tensor<?x?xf32, #encoding_result>)
122+
%0 = linalg.matmul
123+
ins(%lhs, %rhs : tensor<?x?xf32, #encoding_lhs>, tensor<?x?xf32, #encoding_rhs>)
124+
outs(%result : tensor<?x?xf32, #encoding_result>)
221125
-> tensor<?x?xf32, #encoding_result>
222-
iree_tensor_ext.dispatch.tensor.store %6, %2, offsets = [0, 0], sizes = [%M, %N], strides = [1, 1]
223-
: tensor<?x?xf32, #encoding_result>
224-
-> !iree_tensor_ext.dispatch.tensor<readwrite:tensor<?x?xf32, #encoding_result>>{%M, %N}
225-
return
126+
return %0 : tensor<?x?xf32, #encoding_result>
226127
}
227-
// CHECK-DAG: #[[MAP0:.+]] = affine_map<()[s0] -> (s0 ceildiv 8)>
228-
// CHECK-DAG: #[[MAP1:.+]] = affine_map<()[s0] -> (s0 ceildiv 4)>
229-
// CHECK: func @matmul_lowering_f32f32f32_generic()
230-
// CHECK-DAG: %[[C0:.+]] = arith.constant 0 : index
231-
// CHECK-DAG: %[[M:.+]] = hal.interface.constant.load layout({{.+}}) ordinal(0)
232-
// CHECK-DAG: %[[N:.+]] = hal.interface.constant.load layout({{.+}}) ordinal(1)
233-
// CHECK-DAG: %[[K:.+]] = hal.interface.constant.load layout({{.+}}) ordinal(2)
234-
// CHECK-DAG: %[[TILED_M:.+]] = affine.apply #[[MAP0]]()[%[[M]]]
235-
// CHECK-DAG: %[[TILED_K:.+]] = affine.apply #[[MAP1]]()[%[[K]]]
236-
// CHECK: %[[LHS_BINDING:.+]] = hal.interface.binding.subspan layout({{.+}}) binding(0)
237-
// CHECK-SAME: !iree_tensor_ext.dispatch.tensor<readonly:tensor<?x?x8x4xf32>>{%[[TILED_M]], %[[TILED_K]]}
238-
// CHECK: %[[TILED_N:.+]] = affine.apply #[[MAP0]]()[%[[N]]]
239-
// CHECK: %[[RHS_BINDING:.+]] = hal.interface.binding.subspan layout({{.+}}) binding(1)
240-
// CHECK-SAME: !iree_tensor_ext.dispatch.tensor<readonly:tensor<?x?x8x4xf32>>{%[[TILED_N]], %[[TILED_K]]}
241-
// CHECK: %[[OUTS_BINDING:.+]] = hal.interface.binding.subspan layout({{.+}}) binding(2)
242-
// CHECK-SAME: !iree_tensor_ext.dispatch.tensor<readwrite:tensor<?x?x8x8xf32>>{%[[TILED_M]], %[[TILED_N]]}
243-
// CHECK: %[[LHS:.+]] = iree_tensor_ext.dispatch.tensor.load %[[LHS_BINDING]]
244-
// CHECK-SAME: offsets = [0, 0, 0, 0], sizes = [%[[TILED_M]], %[[TILED_K]], 8, 4], strides = [1, 1, 1, 1]
245-
// CHECK: %[[RHS:.+]] = iree_tensor_ext.dispatch.tensor.load %[[RHS_BINDING]]
246-
// CHECK-SAME: offsets = [0, 0, 0, 0], sizes = [%[[TILED_N]], %[[TILED_K]], 8, 4], strides = [1, 1, 1, 1]
247-
// CHECK: %[[OUTS:.+]] = iree_tensor_ext.dispatch.tensor.load %[[OUTS_BINDING]]
248-
// CHECK-SAME: offsets = [0, 0, 0, 0], sizes = [%[[TILED_M]], %[[TILED_N]], 8, 8], strides = [1, 1, 1, 1]
128+
// CHECK: func @matmul_lowering_f32f32f32_generic(
129+
// CHECK-SAME: %[[LHS:[a-zA-Z0-9]+]]: tensor<?x?x8x4xf32>
130+
// CHECK-SAME: %[[RHS:[a-zA-Z0-9]+]]: tensor<?x?x8x4xf32>
131+
// CHECK-SAME: %[[OUTS:[a-zA-Z0-9]+]]: tensor<?x?x8x8xf32>
249132
// CHECK: %[[MMT4D:.+]] = linalg.mmt4d
250133
// CHECK-SAME: ins(%[[LHS]], %[[RHS]] :
251134
// CHECK-SAME: outs(%[[OUTS]] :
252-
// CHECK: iree_tensor_ext.dispatch.tensor.store %[[MMT4D]], %[[OUTS_BINDING]]
253-
// CHECK-SAME: offsets = [0, 0, 0, 0], sizes = [%[[TILED_M]], %[[TILED_N]], 8, 8], strides = [1, 1, 1, 1]
135+
// CHECK: return %[[MMT4D]]

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