fixing whitespace

Author: llysdal

lua/entities/gmod_wire_fpga/cl_init.lua

@@ -25,12 +25,12 @@ function ENT:GetWorldTipBodySize()
   local w,h = surface.GetTextSize(str)
 	w_total = math.max(w_total, w)
   h_total = h_total + h + 10
-  
+
   local str = string.format("peak cpu time: %ius", timebenchPeak * 1000000)
 	local w,h = surface.GetTextSize(str)
 	w_total = math.max(w_total, w)
   h_total = h_total + h + 10
-  
+
 	return w_total, h_total
 end
 
@@ -149,21 +149,21 @@ function ENT:DrawInsideView()
   local scale = math.min(scaleX, scaleY)
 
   local nodeSize = FPGANodeSize/self.ViewData.Scale * scale
-  
+
   --to make sure we don't draw outside the edges
   render.SetScissorRect(
-    FPGAInsideViewPosition[1] + ScrW()/2 + 1, 
-    FPGAInsideViewPosition[3] + ScrH()/2 + 1, 
-    FPGAInsideViewPosition[2] + ScrW()/2 - 1, 
-    FPGAInsideViewPosition[4] + ScrH()/2 - 1, 
+    FPGAInsideViewPosition[1] + ScrW()/2 + 1,
+    FPGAInsideViewPosition[3] + ScrH()/2 + 1,
+    FPGAInsideViewPosition[2] + ScrW()/2 - 1,
+    FPGAInsideViewPosition[4] + ScrH()/2 - 1,
     true
   )
 
   --edges
   for _, edge in pairs(self.ViewData.Edges) do
     surface.SetDrawColor(FPGATypeColor[edge.type])
     surface.DrawLine(
-      centerX + edge.from.x * scale, centerY + edge.from.y * scale, 
+      centerX + edge.from.x * scale, centerY + edge.from.y * scale,
       centerX + edge.to.x * scale, centerY + edge.to.y * scale
     )
   end
@@ -230,7 +230,7 @@ function ENT:ConstructInsideView(viewData)
       size = node.s
     })
   end
-  
+
   self.ViewData.Labels = {}
   if viewData.Labels then
     for _, label in pairs(viewData.Labels) do
@@ -268,7 +268,7 @@ net.Receive("wire_fpga_view_data", function (len)
 
     local ok, data = pcall(util.Decompress, data)
     if not ok then return end
-    
+
     ok, data = pcall(WireLib.von.deserialize, data)
     if ok then
       ent:ConstructInsideView(data)

lua/entities/gmod_wire_fpga/init.lua

@@ -6,7 +6,7 @@ DEFINE_BASECLASS("base_wire_entity")
 
 --HELPERS
 local function getGate(node)
-  if node.type == "wire" then 
+  if node.type == "wire" then
     return GateActions[node.gate]
   elseif node.type == "fpga" then
     return FPGAGateActions[node.gate]
@@ -110,7 +110,7 @@ function ENT:Initialize()
 	self:PhysicsInit(SOLID_VPHYSICS)
 	self:SetMoveType(MOVETYPE_VPHYSICS)
   self:SetSolid(SOLID_VPHYSICS)
-  
+
   self.Debug = false
 
   self.time = 0
@@ -135,7 +135,7 @@ function ENT:Initialize()
 
 	self.Inputs = WireLib.CreateInputs(self, {})
   self.Outputs = WireLib.CreateOutputs(self, {})
-  
+
   self.Gates = {}
   self.LastGateValues = {}
 
@@ -165,7 +165,7 @@ function ENT:BuildDupeInfo()
 end
 
 function ENT:Setup(data)
-  if data then 
+  if data then
     -- entity was duplicated
     self:Upload(data)
   end
@@ -225,14 +225,14 @@ function ENT:SynthesizeViewData(data)
   if not data.Nodes then return end
 
   local viewData = {}
-  
+
   viewData.Nodes = {}
   viewData.Labels = {}
   viewData.Edges = {}
   for nodeId, node in pairs(data.Nodes) do
     local gate = getGate(node)
 
-    if not gate then 
+    if not gate then
       --special case, label
       if node.type == "editor" and node.visual == "label" then
         table.insert(viewData.Labels, {
@@ -331,7 +331,7 @@ function ENT:ValidateData(data)
       end
 
       --type check
-      if getInputType(inGate, inputNum) != getOutputType(outGate, outputNum) then 
+      if getInputType(inGate, inputNum) != getOutputType(outGate, outputNum) then
         return "type mismatch between input and output " .. inGate.name .. " ["..getInputType(inGate, inputNum).."]" .. " and " .. outGate.name .. " ["..getOutputType(outGate, outputNum).."]"
       end
     end
@@ -518,7 +518,7 @@ function ENT:Upload(data)
 
   self.Uploaded = true
 
-  self:Reset()  
+  self:Reset()
 end
 
 
@@ -609,9 +609,9 @@ function ENT:Think()
   BaseClass.Think(self)
 
   if not self.Uploaded then return end
-  if self.CompilationError or self.ExecutionError then 
+  if self.CompilationError or self.ExecutionError then
     self:UpdateOverlay(false)
-    return 
+    return
   end
   self:NextThink(CurTime())
 
@@ -621,7 +621,7 @@ function ENT:Think()
   --Time benchmarking
   self.timebench = self.timebench * 0.98 + (self.time) * 0.02
   self.time = 0
-  
+
   --Limiting
   if self.timebench > fpga_quota_avg then
     self:ThrowExecutionError("exceeded cpu time limit", "cpu time limit exceeded")
@@ -661,7 +661,7 @@ function ENT:Think()
     table.insert(nodesToRun, nodeId)
   end
   self.QueuedNodes = {}
-  
+
   if #nodesToRun > 0 then self:RunProtected(nodesToRun) end
 
   self:UpdateOverlay(false)
@@ -733,7 +733,7 @@ function ENT:Run(changedNodes)
   end
   for nodeId, active in pairs(activeNodes) do
     local gate = getGate(self.Nodes[nodeId])
-    if active and gate.neverActive then 
+    if active and gate.neverActive then
       activeNodes[nodeId] = false
     end
     if gate.alwaysActive then
@@ -763,7 +763,7 @@ function ENT:Run(changedNodes)
   --nodesInQueue = {0, 0, 2, 0, 1, 0, 0, 0, 0, 0, 0, 0}
   --nodesVisited = {}
 
-  if self.Debug then 
+  if self.Debug then
     for nodeId, node in pairs(self.Nodes) do
       print(nodeId .. table.ToString(node, "", false))
     end
@@ -783,7 +783,7 @@ function ENT:Run(changedNodes)
       self:ThrowExecutionError("stuck in loop for too long", "stuck in loop")
       return
     end
-    if self.Debug then 
+    if self.Debug then
       print()
       print(table.ToString(nodeQueue, "nodeQueue", false))
       print(table.ToString(nodesInQueue, "nodesInQueue", false))
@@ -882,7 +882,7 @@ function ENT:Run(changedNodes)
     gate.postCycle(self.Gates[nodeId])
     local value = self:CalculateNode(node, nodeId, gate)
     self:Propagate(node, value)
-  end  
+  end
 
   --keep track of time spent this tick
   self.LastExecution = bench

lua/entities/gmod_wire_fpga/shared.lua

@@ -119,9 +119,9 @@ if SERVER then
       if not IsValid(ply) then continue end --don't know why this happens, but it does
 
       if not ply:KeyDown(IN_USE) then continue end
-      
+
       local ent = ply:GetEyeTrace().Entity
-      
+
       if IsValid(ent) and ent:GetClass() == "gmod_wire_fpga" and ent:AllowsInsideView() and ent:GetViewData() then
         if not FPGAPlayerHasHash[ply] then FPGAPlayerHasHash[ply] = {} end