Merge remote-tracking branch 'wire-cpu/master'

Author: DerelictDrone

addon.json

@@ -15,6 +15,7 @@
 		"git-hooks-pre-commit",
 		"gitrid.sh",
 		"LICENSE",
-		"wiremod.*"
+		"wiremod.*",
+		"benchmark_*"
 	]
 }

data_static/cpuchip/examples/helloworld.txt

@@ -0,0 +1,42 @@
+//Wired Hello World!
+//Connect CPU membus input to console screen
+//Connect CPUs CLK input to button (toggle)
+//Notice how you can store your
+//subroutines/calls in DATA area
+jmp _code;
+message:
+  db 'Hello World!',0;
+WriteString: //ESI - String pointer, EDX - Param
+  mov eax,65536;
+  AWriteLoop:
+    cmp #esi,0; //Terminate on char 0
+    je AEnd;
+    mov #eax,#esi; //Output char
+    inc eax;
+    mov #eax,edx; //Output char param
+    inc eax;
+    inc esi;
+  jmp AWriteLoop;
+  AEnd:
+ret //Return from call
+
+_code:
+  mov esi,message;
+  mov edx,000999; //White foreground on black background
+  call WriteString;
+
+//More about colors:
+//Lower 3 digits are foreground,
+//and higher 3 digits are background
+//Each of 3 digits shows amount of
+//RED, GREEN, and BLUE (in order)
+//Each color has 10 shades - from 0 to 9
+//
+//For example, 999044 will be dark yellow (044) on
+//a white background (999)
+//
+//Experiment with colors!
+//
+//Also, the 7th digit (if its not equal to 0) will
+//cause the character to blink by changing foreground and
+//background places (actual data in memory wont change)

data_static/cpuchip/examples/interrupts.txt

@@ -0,0 +1,109 @@
+/*
+This example assumes you are already familiar with ZASM
+as this will be going over advanced features.
+
+For setup of this example:
+
+1. Wire a button outputting value 32 to the Interrupt input on the CPU
+2. Connect CPU membus input to a console screen
+*/
+
+DATA
+
+/*
+Each external interrupt is 4 bytes
+formatted like so:
+Instruction Pointer, Code Segment, PTB, Flags
+Available flags are
+Bit 3(8)  : Interrupt will set CMPR to 1, unavailable for external interrupts(they restore CMPR on EXTRET)
+Bit 4(16) : Interrupt will not set CS
+Bit 5(32) : Interrupt is enabled
+Bit 6(64) : Interrupt is external
+Bit 7(128): Interrupt will replace page table with PTB, which isn't restored on IRET/EXTRET
+Bit 8(256): Interrupt will replace number of page table entries with PTB, which isn't restored on IRET/EXTRET
+Bit 9(512): Interrupt will also push R0-R31 to stack, use EXTRETA instead of EXTRET to pop them
+
+Flags can be combined, do this by adding the numbers together
+For example:
+8+32 = Interrupt is active, and on interrupt it will set CMPR to 1
+*/
+my_interrupt_table:
+ALLOC 32*4 // The interrupt table is 0 indexed
+DB my_external_interrupt,0,0,96 // so this is index 32
+DB my_internal_interrupt,0,0,32 // and this is index 33
+DB my_timer_interrupt,0,0,96 // Timer interrupts need to be external
+ALLOC 24*4 // Fill rest of space to 58 usable interrupts
+
+external_int_str:
+DB "Hello from External Interrupt!",0
+
+internal_int_str:
+DB "Hello from Internal Interrupt!",0
+
+timer_int_str:
+DB "Hello from the Timer Interrupt",0
+
+my_external_interrupt:
+    CLI // Turn off the ability for another interrupt to happen
+    CPUGET EDI,43 // get external memory and put it in EDI
+    ADD EDI,60    // shift mem offset to start on line 2 of console screen
+    MOV ESI,external_int_str
+    external_int_strcpy: // Copy null terminated string
+        MOV [EDI],[ESI]
+        MCOPY 1
+        MOV [EDI],999 // See helloworld.txt for more information about console colors
+        INC EDI
+        CMP [ESI],0
+    JNE external_int_strcpy
+    CLERR // Clear error code on CPU
+    STI // Re-enable interrupts before returning from interrupt
+EXTRET // You need to use the EXTRET instruction for external interrupts, since IRET only pops IP and CS
+// EXTRET pops all 20 bytes from stack that are generated upon an external interrupt
+
+my_internal_interrupt:
+    // If CLI at start is not present, this interrupt can be interrupted
+    // by another interrupt happening during execution.
+    CPUGET EDI,43 // get external memory and put it in EDI
+    MOV ESI,internal_int_str
+    internal_int_strcpy: // Copy null terminated string
+        MOV [EDI],[ESI]
+        MCOPY 1
+        MOV [EDI],999 // See helloworld.txt for more information about console colors
+        INC EDI
+        CMP [ESI],0
+    JNE internal_int_strcpy
+    CLERR // Clear error code on CPU
+IRET // Registers are not preserved in an internal interrupt, IRET only pops CS and IP to return to
+
+my_timer_interrupt:
+    CLI
+    CPUGET EDI,43 // get external memory and put it in EDI
+    ADD EDI,120   // shift mem offset to start on line 3 of console screen
+    MOV ESI,timer_int_str
+    timer_int_strcpy: // Copy null terminated string
+        MOV [EDI],[ESI]
+        MCOPY 1
+        MOV [EDI],999 // See helloworld.txt for more information about console colors
+        INC EDI
+        CMP [ESI],0
+    JNE timer_int_strcpy
+    CLERR // Clear error code on CPU
+    STI // re-enable interrupts
+EXTRET // Registers are not preserved in an internal interrupt, IRET only pops CS and IP to return to
+
+
+CODE
+STEF // Set the EXTENDED FLAG on, this allows you to call interrupts without halting CPU
+LIDTR my_interrupt_table // Load the interrupt table we have in memory
+CPUSET 52,59 // Set number of interrupts in table (defaults to 256)
+INT 33 // Call interrupt 33 to print to console screen.
+// Note that you can also call external interrupts internally using EXTINT (number)
+CPUSET 67,34 // Set timer interrupt(external interrupt #) to our timer interrupt
+CPUSET 65,4  // Set delay on timer to 4 seconds.
+CPUSET 64,1  // Set timer mode to seconds (it will read the 4 as 4 seconds, set to 2 to read as every 4 instructions)
+// Timer will now be running from here on.
+
+wait_forever:
+INC R0
+JMP wait_forever
+// Use CLEF to disable the extended flag if you want to halt on error instead of handle

data_static/cpuchip/examples/page_rw_override.txt

@@ -0,0 +1,135 @@
+/*
+This example assumes you are already familiar with ZASM
+as this will be going over advanced features.
+
+This will not go too indepth into how the paging
+system works, but instead focus primarily on the feature
+to call an interrupt on read or write of a specific page,
+to intercept memory requests and handle them internally.
+
+Requires CPU memory model to be 8kb ram/rom or above.
+
+For setup of this example:
+
+1. Connect CPU membus input to a console screen
+*/
+
+DATA
+interrupt_table:
+ALLOC 28*4 // fill interrupt space for 0-27
+DB read_mem,0,0,32 // Interrupt 28, called on a delayed memory read
+DB write_mem,0,0,32 // Interrupt 29, called on a delayed memory write
+ALLOC 1*4
+
+page_table:
+ALLOC 16*2 // Entries for the paging table are 2 bytes each.
+
+
+// For more information on interrupts, read the interrupts example
+read_mem:
+CLI
+CLM // Disable paging features temporarily
+    CPUGET ESI,63   // The requested address for the request
+    CPUSET 27,[ESI] // Return the value in LADD
+    CPUSET 42,4     // Set MEMRQ to 4 to signify read was handled
+STM // Reenable paging features after read is performed
+CLERR
+STI
+IRET
+
+write_mem:
+CLI
+    CPUGET EAX,27 // Get value requested for write
+    CPUGET EDI,63 // Requested address for write
+    CPUGET EDX,43 // Internal memory size
+    SUB EDI,128*8 // Subtract page address from it
+    MUL EDI,2 // Force position to be even(char pos)
+    MOV ECX,EDI // Diagonal position
+    MOV EBX,EDI // Horizontal Position
+    MUL EDI,30 // Convert char pos to be line pos instead
+    ADD ECX,EDI // Get diagonal position by adding line to char pos
+
+    // Print vertical character
+    MOV [EDX:EDI],EAX 
+    INC EDI // On odd offsets we need to write color
+    MOV [EDX:EDI],999 // write color to screen
+    // Print horizontal character
+    MOV [EDX:EBX],EAX
+    INC EBX
+    MOV [EDX:EBX],999
+    // Print diagonal character
+    MOV [EDX:ECX],EAX
+    INC ECX
+    MOV [EDX:ECX],999
+
+    CPUGET EAX,28 // Get LINT to check if we failed any memory I/O
+    CMP EAX,29 // Check if we're in our own interrupt
+    JNE shutdown
+    CPUSET 42,5   // Set MEMRQ to 5 to signify write was handled
+CLERR
+STI
+IRET
+
+shutdown:
+STI
+CLM
+CLEF
+INT EAX // repeat error now that we're not in extended mode
+
+CODE
+STEF // Set extended flag for interrupt handling
+CPUSET 37,page_table // Load page table ptr into PTBL register
+CPUSET 38,16 // Set page table entries in PTBE register
+LIDTR interrupt_table
+
+MOV EAX,0
+// Since only Readable/Writable/Executable are accessible via
+// the SPP Instruction, we have to manually create a permissions
+// mask for our new pages.
+
+// Using SBIT isn't entirely necessary, to get the number below you can also
+// use the constant 232(calculated from 8+32+64+128)
+SBIT EAX,3 // (8)   Read & Write calls int 28(read) and int 29(write)
+SBIT EAX,5 // (32)  Readable
+SBIT EAX,6 // (64)  Writable
+SBIT EAX,7 // (128) Executable
+ADD EAX,(256*2)
+// Runlevel can be obtained from the permission mask with floor(pmask/256)%256
+// To set the runlevel, add 256*runlevel to the permission mask
+MOV ECX,3 // Set 2 pages
+MOV EBX,7*2 // Starting from page 8
+ADD EBX,page_table
+
+page_set_loop:
+    MOV EDI,ECX
+    MUL EDI,2
+    MOV [EBX:EDI],EAX // Page byte 0 is the permission mask of the page
+    INC EDI // Access page byte 1
+    MOV [EBX:EDI],0 // Page byte 1 is the page this redirects to if the mapped flag is set
+LOOP page_set_loop
+
+STM // Set Memory flag to enable memory paging features
+
+/*
+Note that, unlike regular console screen prints
+this doesn't need to write character to even indexes
+and color to odd indexes, since those are both handled
+by interrupt 29(write_mem), so we can treat this like
+a regular section of memory.
+*/
+
+MOV R0,128*8 // Get first index of page 8
+MOV ESI,str
+
+print_loop:
+MOV [R0],[ESI]
+INC R0
+INC ESI
+CMP [ESI],0
+JNE print_loop
+
+CLEF // Disable interrupt handling
+INT 2 // End execution.
+
+str:
+DB "Hello Wiremod!",0

data_static/cpuchip/examples/segments.txt

@@ -0,0 +1,91 @@
+/*
+This example assumes you are already familiar with ZASM
+as this will be going over semi-advanced features.
+
+Segment registers allow you to add an offset to memory access
+By default, they are all set to 0 on first startup of CPU
+and reset to 0 when the CPU is reset.
+
+The available segment registers are
+CS - Code Segment, used to read instructions from RAM.
+     It can only be changed with far jump instructions, trying to
+     set it using other instructions results in an error of #13[1]
+
+     Setting this allows compiled programs using branches to run
+     without having to be compiled knowing where they will sit in
+     memory
+
+SS - Stack Segment, this is where the stack starts from, stack access
+     via PUSH, POP, RSTACK, SSTACK is relative to this segment
+
+DS - Data Segment, default for all memory access instructions
+     unless another segment is specified.
+
+User Segments, none of these are used internally, so they can be used
+without fear of altering behavior outside of user programs which use
+these segments
+ES - Extra Segment
+GS - "G Segment"
+FS - "F Segment"
+KS - Key Segment
+LS - Library Segment
+*/
+
+// Segment registers can be read and written to like any other register
+start:
+MOV DS,data_pos
+MOV R0,3
+MOV R1,[R0] // 3+data_pos, aka the fourth value, 720. Doesn't change R0
+            // or DS in order to access and store the value in R1
+MOV R2,[0]  // 0+data_pos, aka the first value, 640.
+JMP end_data_pos
+data_pos:
+DB 640,480
+DB 1280,720
+DB 0
+end_data_pos:
+
+MOV R3,[CS:0]  // Segment for access can be specified with SEG:Value
+MOV R4,[EAX:0] // and any register can be used as a segment
+MOV R5,R0:0    // This does nothing
+
+/*
+LEA is one of the few instructions that use a user defined segment
+outside of memory access, and it writes the value of the address used
+by a memory access to the left hand side, it is effectively the same as
+
+MOV EAX,R0 //(EAX is just a standin for an unused register)
+ADD EAX,DS //(or the segment explicitly defined instead of DS)
+MOV R7,EAX
+
+^
+this code uses 6 bytes, where LEA uses:
+2 bytes(no segment supplied, register to register transfer I.E LEA R7,R0)
+3 bytes(segment supplied by user, register to register transfer I.E LEA R7,SS:R0)
+
+*/ 
+
+LEA R6,[R0]    // This will put DS+R0 into R6 (data_pos+3)
+LEA R7,[SS:R0] // This will put SS+R0 into R7(SS+3)
+
+/*
+Wire your CPU to a memory device
+and upload your own program to the device
+by clicking on it as if it were a CPU
+ 
+If this example is uploaded to your CPU
+it will begin running the code on the
+memory device as if it were running on
+the original CPU, to debug the program
+press compile with your code open in the
+editor, afterward "Step Forward" will begin
+showing the proper lines.
+*/
+
+CPUGET DS,43 // Get RAM size of CPU, aka the first byte of external memory.
+JMPF 0,DS   // JMP to 0 + DS, setting CS to DS
+
+/*
+Your program will now run from here until
+it errors or you reset it.
+*/