diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi index aca22a7f0191c..4791e1fd7c20f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi @@ -7,6 +7,13 @@ nvmem-cells = <&cpu_speed_grade>; opp-shared; + opp-288000000 { + opp-hz = /bits/ 64 <288000000>; + opp-microvolt = <900000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x1f>; + }; + opp-480000000 { opp-hz = /bits/ 64 <480000000>; opp-microvolt = <900000>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-wirenboard8xx.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-wirenboard8xx.dtsi index 8601b06607b1e..d26ae0e56283d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-wirenboard8xx.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-wirenboard8xx.dtsi @@ -460,6 +460,143 @@ status = "okay"; }; }; + + thermal-zones { + /* + target minimum lifetime is 100 000 hours or ~11.5 years. + As per T517 chip lifetime evaluation guide, it corresponds to + junction temperature of: + 125C @ 0.900V (note it's also absolute maximum Tj) + 115С @ 0.950V (not in the source, intrapolated) + 105C @ 1.000V + 95C @ 1.050V + 85C @ 1.100V (not in the source, extrapolated) + + Taking into account that the temperature sensor accuracy is + ±3°C from 0°C to +100°C, ±5°C from -25°C to +125°C Tj, max allowed + junction temperature should be: + 120C @ 0.900V + 110C @ 0.950V + 100C @ 1.000V (lower voltage to below 1.0V once hit 100C) + 92C @ 1.050V (lower voltage to below 1.05V once hit 92C) + 82C @ 1.100V (lower voltage to below 1.1V once hit 82C) + */ + cpu-thermal { + sustainable-power = <1100>; + + k_po = <45>; + k_pu = <90>; + k_i = <0>; + /delete-node/ trips; + /delete-node/ cooling-maps; + + trips { + cpu_max_for_1100mv: cpu-trip-0 { + temperature = <82000>; + type = "passive"; + hysteresis = <500>; + }; + cpu_max_for_1050mv: cpu-trip-1 { + temperature = <92000>; + type = "passive"; + hysteresis = <500>; + }; + + cpu_max_for_1000mv: cpu-trip-2 { + temperature = <100000>; + type = "passive"; + hysteresis = <500>; + }; + + cpu_max_for_950mv: cpu-trip-3 { + temperature = <110000>; + type = "passive"; + hysteresis = <500>; + }; + + + cpu_critical: cpu-trip-4 { + /* + 120C is the maximum recommended Tj, + temperature sensor accuracy is +/-5C @ Tj>100C + so we should not exceed 115C just in case + */ + temperature = <115000>; + type = "critical"; + hysteresis = <0>; + }; + }; + cooling-maps { + /* + The OPP voltages depends on revision and speed grade. + Anyway: + 2: 1200 MHz, 1.02V - 1.10V, 1.05V on ours + 3: 1104 MHz, 1.00V (use it to go lower than 1.05V) + 4: 1008 MHz, 0.94V - 1.02V, 0.95V on ours + 5: 936 MHz, 0.90V (lowest voltage, allowed at any Tj) + 6: 720 MHz, 0.90V + */ + + /* + The first two maps are to limit the voltage. + That's why we don't allow lower frequencies on the cooling device. + */ + map0 { + trip = <&cpu_max_for_1100mv>; + cooling-device = <&cpu0 2 2>, + <&cpu1 2 2>, + <&cpu2 2 2>, + <&cpu3 2 2>; + }; + + map1 { + trip = <&cpu_max_for_1050mv>; + cooling-device = <&cpu0 3 3>, + <&cpu1 3 3>, + <&cpu2 3 3>, + <&cpu3 3 3>; + }; + + /* + This is our target temperature point. + We nevertheless limit the frequency to 480 MHz, so the performace + is not too low. + */ + map2 { + trip = <&cpu_max_for_1000mv>; + cooling-device = <&cpu0 4 7>, + <&cpu1 4 7>, + <&cpu2 4 7>, + <&cpu3 4 7>; + }; + + /* + At this point we should do everything to maintain the temperature. + */ + map3 { + trip = <&cpu_max_for_950mv>; + cooling-device = <&cpu0 5 THERMAL_NO_LIMIT>, + <&cpu1 5 THERMAL_NO_LIMIT>, + <&cpu2 5 THERMAL_NO_LIMIT>, + <&cpu3 5 THERMAL_NO_LIMIT>, + /* don't inject idle to CPU0 so it's available for kernel tasks */ + <&cpu1idle THERMAL_NO_LIMIT 90>, + <&cpu2idle THERMAL_NO_LIMIT 90>, + <&cpu3idle THERMAL_NO_LIMIT 90>; }; + }; + }; + }; +}; + +// override GPU, VE and DDR critical temperatures +&gpu_temp_critical { + temperature = <115000>; +}; +&ve_temp_critical { + temperature = <115000>; +}; +&ddr_temp_critical { + temperature = <115000>; }; &spi1 { @@ -881,7 +1018,6 @@ regulator-max-microvolt = <1800000>; regulator-step-delay-us = <25>; regulator-final-delay-us = <50>; - regulator-always-on; }; reg_bldo5: bldo5 { @@ -898,7 +1034,6 @@ regulator-max-microvolt = <3300000>; regulator-step-delay-us = <25>; regulator-final-delay-us = <50>; - regulator-always-on; }; reg_cldo2: cldo2 { @@ -907,7 +1042,6 @@ regulator-max-microvolt = <1800000>; regulator-step-delay-us = <25>; regulator-final-delay-us = <50>; - regulator-always-on; }; reg_cldo3: cldo3 { diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index 8435aec0f8c2a..59a72bfba76c6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -27,6 +27,14 @@ enable-method = "psci"; clocks = <&ccu CLK_CPUX>; #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; + dynamic-power-coefficient = <100>; + + cpu0idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; + }; }; cpu1: cpu@1 { @@ -36,6 +44,13 @@ enable-method = "psci"; clocks = <&ccu CLK_CPUX>; #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; + + cpu1idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; + }; }; cpu2: cpu@2 { @@ -45,6 +60,13 @@ enable-method = "psci"; clocks = <&ccu CLK_CPUX>; #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; + + cpu2idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; + }; }; cpu3: cpu@3 { @@ -54,6 +76,25 @@ enable-method = "psci"; clocks = <&ccu CLK_CPUX>; #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; + + cpu3idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; + }; + }; + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <120>; + exit-latency-us = <250>; + min-residency-us = <900>; + }; }; }; diff --git a/arch/arm64/configs/wb8_reduced_defconfig b/arch/arm64/configs/wb8_reduced_defconfig index 836caf2397dbd..17daa2cb66f8e 100644 --- a/arch/arm64/configs/wb8_reduced_defconfig +++ b/arch/arm64/configs/wb8_reduced_defconfig @@ -212,6 +212,8 @@ CONFIG_DM_ZERO=m CONFIG_NETDEVICES=y CONFIG_MACVLAN=m CONFIG_MACVTAP=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_TUN=y CONFIG_VETH=m CONFIG_VIRTIO_NET=y @@ -397,8 +399,14 @@ CONFIG_SENSORS_LM90=m CONFIG_SENSORS_PWM_FAN=m CONFIG_SENSORS_INA2XX=m CONFIG_SENSORS_INA3221=m +CONFIG_THERMAL_NETLINK=y +CONFIG_THERMAL_STATISTICS=y +CONFIG_THERMAL_DEBUGFS=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=5000 +CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_CPU_THERMAL=y +CONFIG_CPU_IDLE_THERMAL=y CONFIG_DEVFREQ_THERMAL=y CONFIG_THERMAL_EMULATION=y CONFIG_SUN8I_THERMAL=y @@ -697,6 +705,9 @@ CONFIG_PHY_CADENCE_TORRENT=m CONFIG_PHY_CADENCE_SIERRA=m CONFIG_PHY_QCOM_USB_HS=m CONFIG_PHY_SAMSUNG_USB2=y +CONFIG_POWERCAP=y +CONFIG_IDLE_INJECT=y +CONFIG_ARM_SCMI_POWERCAP=y CONFIG_ARM_CCI_PMU=m CONFIG_ARM_CCN=m CONFIG_ARM_CMN=m