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urishurish
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feat(eeprom): implement EEPROM peripheral
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6 files changed

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6 files changed

+408
-42
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‎src/index.ts‎

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@@ -26,4 +26,11 @@ export {
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PinState,
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} from './peripherals/gpio';
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export { AVRUSART, usart0Config } from './peripherals/usart';
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export {
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AVREEPROM,
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AVREEPROMConfig,
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EEPROMBackend,
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EEPROMMemoryBackend,
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eepromConfig,
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} from './peripherals/eeprom';
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export * from './peripherals/twi';

‎src/peripherals/eeprom.spec.ts‎

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import { CPU } from '../cpu/cpu';
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import { AVREEPROM, EEPROMMemoryBackend } from './eeprom';
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import { asmProgram, TestProgramRunner } from '../utils/test-utils';
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// EEPROM Registers
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const EECR = 0x3f;
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const EEDR = 0x40;
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const EEARL = 0x41;
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const EEARH = 0x42;
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const SREG = 95;
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// Register bit names
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/* eslint-disable @typescript-eslint/no-unused-vars */
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const EERE = 1;
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const EEPE = 2;
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const EEMPE = 4;
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const EERIE = 8;
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const EEPM0 = 16;
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const EEPM1 = 32;
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/* eslint-enable @typescript-eslint/no-unused-vars */
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describe('EEPROM', () => {
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describe('Reading the EEPROM', () => {
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it('should return 0xff when reading from an empty location', () => {
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const cpu = new CPU(new Uint16Array(0x1000));
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const eeprom = new AVREEPROM(cpu, new EEPROMMemoryBackend(1024));
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cpu.writeData(EEARL, 0);
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cpu.writeData(EEARH, 0);
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cpu.writeData(EECR, EERE);
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eeprom.tick();
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expect(cpu.cycles).toEqual(4);
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expect(cpu.data[EEDR]).toEqual(0xff);
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});
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it('should return the value stored at the given EEPROM address', () => {
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const cpu = new CPU(new Uint16Array(0x1000));
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const eepromBackend = new EEPROMMemoryBackend(1024);
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const eeprom = new AVREEPROM(cpu, eepromBackend);
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eepromBackend.memory[0x250] = 0x42;
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cpu.writeData(EEARL, 0x50);
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cpu.writeData(EEARH, 0x2);
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cpu.writeData(EECR, EERE);
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eeprom.tick();
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expect(cpu.data[EEDR]).toEqual(0x42);
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});
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});
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describe('Writing to the EEPROM', () => {
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it('should write a byte to the given EEPROM address', () => {
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const cpu = new CPU(new Uint16Array(0x1000));
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const eepromBackend = new EEPROMMemoryBackend(1024);
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const eeprom = new AVREEPROM(cpu, eepromBackend);
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cpu.writeData(EEDR, 0x55);
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cpu.writeData(EEARL, 15);
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cpu.writeData(EEARH, 0);
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cpu.writeData(EECR, EEMPE);
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cpu.writeData(EECR, EEPE);
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eeprom.tick();
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expect(cpu.cycles).toEqual(2);
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expect(eepromBackend.memory[15]).toEqual(0x55);
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expect(cpu.data[EECR] & EEPE).toEqual(EEPE);
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});
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it('should not erase the memory when writing if EEPM1 is high', () => {
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// We subtract 0x20 to translate from RAM address space to I/O register space
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const { program } = asmProgram(`
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; register addresses
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_REPLACE TWSR, ${EECR - 0x20}
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_REPLACE EEARL, ${EEARL - 0x20}
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_REPLACE EEDR, ${EEDR - 0x20}
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_REPLACE EECR, ${EECR - 0x20}
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LDI r16, 0x55
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OUT EEDR, r16
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LDI r16, 9
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OUT EEARL, r16
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SBI EECR, 5 ; EECR |= EEPM1
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SBI EECR, 2 ; EECR |= EEMPE
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SBI EECR, 1 ; EECR |= EEPE
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`);
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const cpu = new CPU(program);
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const eepromBackend = new EEPROMMemoryBackend(1024);
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const eeprom = new AVREEPROM(cpu, eepromBackend);
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eepromBackend.memory[9] = 0x0f; // high four bits are cleared
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const runner = new TestProgramRunner(cpu, eeprom);
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runner.runInstructions(program.length);
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// EEPROM was 0x0f, and our program wrote 0x55.
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// Since write (without erase) only clears bits, we expect 0x05 now.
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expect(eepromBackend.memory[9]).toEqual(0x05);
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});
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it('should clear the EEPE bit and fire an interrupt when write has been completed', () => {
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const cpu = new CPU(new Uint16Array(0x1000));
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const eepromBackend = new EEPROMMemoryBackend(1024);
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const eeprom = new AVREEPROM(cpu, eepromBackend);
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cpu.writeData(EEDR, 0x55);
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cpu.writeData(EEARL, 15);
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cpu.writeData(EEARH, 0);
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cpu.writeData(EECR, EEMPE | EERIE);
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cpu.data[SREG] = 0x80; // SREG: I-------
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cpu.writeData(EECR, EEPE);
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cpu.cycles += 1000;
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eeprom.tick();
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// At this point, write shouldn't be complete yet
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expect(cpu.data[EECR] & EEPE).toEqual(EEPE);
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expect(cpu.pc).toEqual(0);
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cpu.cycles += 10000000;
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// And now, 10 million cycles later, it should.
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eeprom.tick();
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expect(eepromBackend.memory[15]).toEqual(0x55);
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expect(cpu.data[EECR] & EEPE).toEqual(0);
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expect(cpu.pc).toEqual(0x2c); // EEPROM Ready interrupt
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});
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it('should skip the write if EEMPE is clear', () => {
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const cpu = new CPU(new Uint16Array(0x1000));
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const eepromBackend = new EEPROMMemoryBackend(1024);
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const eeprom = new AVREEPROM(cpu, eepromBackend);
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cpu.writeData(EEDR, 0x55);
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cpu.writeData(EEARL, 15);
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cpu.writeData(EEARH, 0);
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cpu.writeData(EECR, EEMPE);
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cpu.cycles = 8; // waiting for more than 4 cycles should clear EEMPE
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eeprom.tick();
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cpu.writeData(EECR, EEPE);
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eeprom.tick();
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// Ensure that nothing was written, and EEPE bit is clear
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expect(cpu.cycles).toEqual(8);
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expect(eepromBackend.memory[15]).toEqual(0xff);
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expect(cpu.data[EECR] & EEPE).toEqual(0);
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});
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it('should skip the write if another write is already in progress', () => {
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const cpu = new CPU(new Uint16Array(0x1000));
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const eepromBackend = new EEPROMMemoryBackend(1024);
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const eeprom = new AVREEPROM(cpu, eepromBackend);
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// Write 0x55 to address 15
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cpu.writeData(EEDR, 0x55);
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cpu.writeData(EEARL, 15);
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cpu.writeData(EEARH, 0);
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cpu.writeData(EECR, EEMPE);
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cpu.writeData(EECR, EEPE);
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eeprom.tick();
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expect(cpu.cycles).toEqual(2);
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// Write 0x66 to address 16 (first write is still in progress)
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cpu.writeData(EEDR, 0x66);
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cpu.writeData(EEARL, 16);
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cpu.writeData(EEARH, 0);
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cpu.writeData(EECR, EEMPE);
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cpu.writeData(EECR, EEPE);
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eeprom.tick();
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// Ensure that second write didn't happen
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expect(cpu.cycles).toEqual(2);
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expect(eepromBackend.memory[15]).toEqual(0x55);
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expect(eepromBackend.memory[16]).toEqual(0xff);
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});
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});
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describe('EEPROM erase', () => {
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it('should only erase the memory when EEPM0 is high', () => {
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// We subtract 0x20 to translate from RAM address space to I/O register space
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const { program } = asmProgram(`
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; register addresses
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_REPLACE TWSR, ${EECR - 0x20}
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_REPLACE EEARL, ${EEARL - 0x20}
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_REPLACE EEDR, ${EEDR - 0x20}
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_REPLACE EECR, ${EECR - 0x20}
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LDI r16, 0x55
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OUT EEDR, r16
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LDI r16, 9
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OUT EEARL, r16
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SBI EECR, 4 ; EECR |= EEPM0
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SBI EECR, 2 ; EECR |= EEMPE
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SBI EECR, 1 ; EECR |= EEPE
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`);
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const cpu = new CPU(program);
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const eepromBackend = new EEPROMMemoryBackend(1024);
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const eeprom = new AVREEPROM(cpu, eepromBackend);
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eepromBackend.memory[9] = 0x22;
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const runner = new TestProgramRunner(cpu, eeprom);
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runner.runInstructions(program.length);
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expect(eepromBackend.memory[9]).toEqual(0xff);
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});
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});
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});

‎src/peripherals/eeprom.ts‎

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import { CPU } from '../cpu/cpu';
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import { avrInterrupt } from '../cpu/interrupt';
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import { u8, u16, u32 } from '../types';
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export interface EEPROMBackend {
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readMemory(addr: u16): u8;
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writeMemory(addr: u16, value: u8): void;
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eraseMemory(addr: u16): void;
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}
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export class EEPROMMemoryBackend implements EEPROMBackend {
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readonly memory: Uint8Array;
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constructor(size: u16) {
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this.memory = new Uint8Array(size);
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this.memory.fill(0xff);
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}
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readMemory(addr: u16) {
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return this.memory[addr];
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}
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writeMemory(addr: u16, value: u8) {
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this.memory[addr] &= value;
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}
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eraseMemory(addr: u16) {
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this.memory[addr] = 0xff;
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}
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}
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export interface AVREEPROMConfig {
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eepromReadyInterrupt: u8;
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EECR: u8;
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EEDR: u8;
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EEARL: u8;
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EEARH: u8;
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/** The amount of clock cycles erase takes */
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eraseCycles: u32;
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/** The amount of clock cycles a write takes */
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writeCycles: u32;
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}
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export const eepromConfig: AVREEPROMConfig = {
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eepromReadyInterrupt: 0x2c,
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EECR: 0x3f,
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EEDR: 0x40,
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EEARL: 0x41,
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EEARH: 0x42,
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eraseCycles: 28800, // 1.8ms at 16MHz
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writeCycles: 28800, // 1.8ms at 16MHz
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};
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const EERE = 1 << 0;
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const EEPE = 1 << 1;
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const EEMPE = 1 << 2;
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const EERIE = 1 << 3;
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const EEPM0 = 1 << 4;
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const EEPM1 = 1 << 5;
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export class AVREEPROM {
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/**
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* Used to keep track on the last write to EEMPE. From the datasheet:
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* The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written.
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* When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM
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* at the selected address If EEMPE is zero, setting EEPE will have no effect.
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*/
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private writeEnabledCycles = 0;
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private writeCompleteCycles = 0;
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constructor(
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private cpu: CPU,
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private backend: EEPROMBackend,
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private config: AVREEPROMConfig = eepromConfig
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) {
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this.cpu.writeHooks[this.config.EECR] = (eecr) => {
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const { EEARH, EEARL, EECR, EEDR } = this.config;
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const addr = (this.cpu.data[EEARH] << 8) | this.cpu.data[EEARL];
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if (eecr & EEMPE) {
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this.writeEnabledCycles = this.cpu.cycles + 4;
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}
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// Read
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if (eecr & EERE) {
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this.cpu.data[EEDR] = this.backend.readMemory(addr);
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// When the EEPROM is read, the CPU is halted for four cycles before the
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// next instruction is executed.
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this.cpu.cycles += 4;
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return true;
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}
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// Write
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if (eecr & EEPE) {
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// If EEMPE is zero, setting EEPE will have no effect.
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if (this.cpu.cycles >= this.writeEnabledCycles) {
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return true;
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}
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// Check for write-in-progress
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if (this.writeCompleteCycles) {
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return true;
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}
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const eedr = this.cpu.data[EEDR];
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this.writeCompleteCycles = this.cpu.cycles;
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// Erase
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if (!(eecr & EEPM1)) {
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this.backend.eraseMemory(addr);
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this.writeCompleteCycles += this.config.eraseCycles;
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}
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// Write
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if (!(eecr & EEPM0)) {
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this.backend.writeMemory(addr, eedr);
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this.writeCompleteCycles += this.config.writeCycles;
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}
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this.cpu.data[EECR] |= EEPE;
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// When EEPE has been set, the CPU is halted for two cycles before the
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// next instruction is executed.
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this.cpu.cycles += 2;
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return true;
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}
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return false;
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};
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}
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tick() {
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const { EECR, eepromReadyInterrupt } = this.config;
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if (this.writeEnabledCycles && this.cpu.cycles > this.writeEnabledCycles) {
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this.cpu.data[EECR] &= ~EEMPE;
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}
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if (this.writeCompleteCycles && this.cpu.cycles > this.writeCompleteCycles) {
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this.cpu.data[EECR] &= ~EEPE;
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if (this.cpu.interruptsEnabled && this.cpu.data[EECR] & EERIE) {
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avrInterrupt(this.cpu, eepromReadyInterrupt);
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}
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}
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}
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}

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