refactor: central interrupt handling #38

Author: urish

demo/src/execute.ts

@@ -54,6 +54,7 @@ export class AVRRunner {
       this.timer1.tick();
       this.timer2.tick();
       this.usart.tick();
+      this.cpu.tick();
     }
 
     callback(this.cpu);

src/cpu/cpu.ts

@@ -5,7 +5,8 @@
  * Copyright (C) 2019, Uri Shaked
  */
 
-import { u32, u16, u8 } from '../types';
+import { u32, u16, u8, i16 } from '../types';
+import { avrInterrupt } from './interrupt';
 
 const registerSpace = 0x100;
 
@@ -45,20 +46,31 @@ export interface CPUMemoryReadHooks {
   [key: number]: CPUMemoryReadHook;
 }
 
+export interface AVRInterruptConfig {
+  address: u8;
+  enableRegister: u16;
+  enableMask: u8;
+  flagRegister: u16;
+  flagMask: u8;
+  constant?: boolean;
+}
+
 export class CPU implements ICPU {
   readonly data: Uint8Array = new Uint8Array(this.sramBytes + registerSpace);
   readonly data16 = new Uint16Array(this.data.buffer);
   readonly dataView = new DataView(this.data.buffer);
   readonly progBytes = new Uint8Array(this.progMem.buffer);
   readonly readHooks: CPUMemoryReadHooks = [];
   readonly writeHooks: CPUMemoryHooks = [];
+  private readonly pendingInterrupts: AVRInterruptConfig[] = [];
   readonly pc22Bits = this.progBytes.length > 0x20000;
 
   // This lets the Timer Compare output override GPIO pins:
   readonly gpioTimerHooks: CPUMemoryHooks = [];
 
-  pc = 0;
-  cycles = 0;
+  pc: u32 = 0;
+  cycles: u32 = 0;
+  nextInterrupt: i16 = -1;
 
   constructor(public progMem: Uint16Array, private sramBytes = 8192) {
     this.reset();
@@ -67,6 +79,8 @@ export class CPU implements ICPU {
   reset() {
     this.data.fill(0);
     this.SP = this.data.length - 1;
+    this.pendingInterrupts.splice(0, this.pendingInterrupts.length);
+    this.nextInterrupt = -1;
   }
 
   readData(addr: number) {
@@ -101,4 +115,63 @@ export class CPU implements ICPU {
   get interruptsEnabled() {
     return this.SREG & 0x80 ? true : false;
   }
+
+  private updateNextInterrupt() {
+    this.nextInterrupt = this.pendingInterrupts.findIndex((item) => !!item);
+  }
+
+  setInterruptFlag(interrupt: AVRInterruptConfig) {
+    const { flagRegister, flagMask, enableRegister, enableMask } = interrupt;
+    if (interrupt.constant) {
+      this.data[flagRegister] &= ~flagMask;
+    } else {
+      this.data[flagRegister] |= flagMask;
+    }
+    if (this.data[enableRegister] & enableMask) {
+      this.queueInterrupt(interrupt);
+    }
+  }
+
+  updateInterruptEnable(interrupt: AVRInterruptConfig, registerValue: u8) {
+    const { enableMask, flagRegister, flagMask } = interrupt;
+    if (registerValue & enableMask) {
+      if (this.data[flagRegister] & flagMask) {
+        this.queueInterrupt(interrupt);
+      }
+    } else {
+      this.clearInterrupt(interrupt, false);
+    }
+  }
+
+  queueInterrupt(interrupt: AVRInterruptConfig) {
+    this.pendingInterrupts[interrupt.address] = interrupt;
+    this.updateNextInterrupt();
+  }
+
+  clearInterrupt({ address, flagRegister, flagMask }: AVRInterruptConfig, clearFlag = true) {
+    delete this.pendingInterrupts[address];
+    if (clearFlag) {
+      this.data[flagRegister] &= ~flagMask;
+    }
+    this.updateNextInterrupt();
+  }
+
+  clearInterruptByFlag(interrupt: AVRInterruptConfig, registerValue: number) {
+    const { flagRegister, flagMask } = interrupt;
+    if (registerValue & flagMask) {
+      this.data[flagRegister] &= ~flagMask;
+      this.clearInterrupt(interrupt);
+    }
+  }
+
+  tick() {
+    if (this.interruptsEnabled && this.nextInterrupt >= 0) {
+      const interrupt = this.pendingInterrupts[this.nextInterrupt];
+      // eslint-disable-next-line @typescript-eslint/no-non-null-assertion
+      avrInterrupt(this, interrupt.address);
+      if (!interrupt.constant) {
+        this.clearInterrupt(interrupt);
+      }
+    }
+  }
 }

src/peripherals/eeprom.spec.ts

@@ -28,6 +28,7 @@ describe('EEPROM', () => {
       cpu.writeData(EEARH, 0);
       cpu.writeData(EECR, EERE);
       eeprom.tick();
+      cpu.tick();
       expect(cpu.cycles).toEqual(4);
       expect(cpu.data[EEDR]).toEqual(0xff);
     });
@@ -41,6 +42,7 @@ describe('EEPROM', () => {
       cpu.writeData(EEARH, 0x2);
       cpu.writeData(EECR, EERE);
       eeprom.tick();
+      cpu.tick();
       expect(cpu.data[EEDR]).toEqual(0x42);
     });
   });
@@ -56,6 +58,7 @@ describe('EEPROM', () => {
       cpu.writeData(EECR, EEMPE);
       cpu.writeData(EECR, EEPE);
       eeprom.tick();
+      cpu.tick();
       expect(cpu.cycles).toEqual(2);
       expect(eepromBackend.memory[15]).toEqual(0x55);
       expect(cpu.data[EECR] & EEPE).toEqual(EEPE);
@@ -104,12 +107,14 @@ describe('EEPROM', () => {
       cpu.writeData(EECR, EEPE);
       cpu.cycles += 1000;
       eeprom.tick();
+      cpu.tick();
       // At this point, write shouldn't be complete yet
       expect(cpu.data[EECR] & EEPE).toEqual(EEPE);
       expect(cpu.pc).toEqual(0);
       cpu.cycles += 10000000;
       // And now, 10 million cycles later, it should.
       eeprom.tick();
+      cpu.tick();
       expect(eepromBackend.memory[15]).toEqual(0x55);
       expect(cpu.data[EECR] & EEPE).toEqual(0);
       expect(cpu.pc).toEqual(0x2c); // EEPROM Ready interrupt
@@ -125,8 +130,10 @@ describe('EEPROM', () => {
       cpu.writeData(EECR, EEMPE);
       cpu.cycles = 8; // waiting for more than 4 cycles should clear EEMPE
       eeprom.tick();
+      cpu.tick();
       cpu.writeData(EECR, EEPE);
       eeprom.tick();
+      cpu.tick();
       // Ensure that nothing was written, and EEPE bit is clear
       expect(cpu.cycles).toEqual(8);
       expect(eepromBackend.memory[15]).toEqual(0xff);
@@ -145,6 +152,7 @@ describe('EEPROM', () => {
       cpu.writeData(EECR, EEMPE);
       cpu.writeData(EECR, EEPE);
       eeprom.tick();
+      cpu.tick();
       expect(cpu.cycles).toEqual(2);
 
       // Write 0x66 to address 16 (first write is still in progress)
@@ -154,6 +162,7 @@ describe('EEPROM', () => {
       cpu.writeData(EECR, EEMPE);
       cpu.writeData(EECR, EEPE);
       eeprom.tick();
+      cpu.tick();
 
       // Ensure that second write didn't happen
       expect(cpu.cycles).toEqual(2);
@@ -173,11 +182,13 @@ describe('EEPROM', () => {
       cpu.writeData(EECR, EEMPE);
       cpu.writeData(EECR, EEPE);
       eeprom.tick();
+      cpu.tick();
       expect(cpu.cycles).toEqual(2);
 
       // wait long enough time for the first write to finish
       cpu.cycles += 10000000;
       eeprom.tick();
+      cpu.tick();
 
       // Write 0x66 to address 16
       cpu.writeData(EEDR, 0x66);
@@ -186,6 +197,7 @@ describe('EEPROM', () => {
       cpu.writeData(EECR, EEMPE);
       cpu.writeData(EECR, EEPE);
       eeprom.tick();
+      cpu.tick();
 
       // Ensure both writes took place
       expect(cpu.cycles).toEqual(10000004);

src/peripherals/eeprom.ts

@@ -1,6 +1,5 @@
-import { CPU } from '../cpu/cpu';
-import { avrInterrupt } from '../cpu/interrupt';
-import { u8, u16, u32 } from '../types';
+import { AVRInterruptConfig, CPU } from '../cpu/cpu';
+import { u16, u32, u8 } from '../types';
 
 export interface EEPROMBackend {
   readMemory(addr: u16): u8;
@@ -71,6 +70,16 @@ export class AVREEPROM {
 
   private writeCompleteCycles = 0;
 
+  // Interrupts
+  private EER: AVRInterruptConfig = {
+    address: this.config.eepromReadyInterrupt,
+    flagRegister: this.config.EECR,
+    flagMask: EEPE,
+    enableRegister: this.config.EECR,
+    enableMask: EERIE,
+    constant: true,
+  };
+
   constructor(
     private cpu: CPU,
     private backend: EEPROMBackend,
@@ -81,6 +90,10 @@ export class AVREEPROM {
 
       const addr = (this.cpu.data[EEARH] << 8) | this.cpu.data[EEARL];
 
+      if (eecr & EERE) {
+        this.cpu.clearInterrupt(this.EER);
+      }
+
       if (eecr & EEMPE) {
         this.writeEnabledCycles = this.cpu.cycles + 4;
       }
@@ -132,16 +145,13 @@ export class AVREEPROM {
   }
 
   tick() {
-    const { EECR, eepromReadyInterrupt } = this.config;
+    const { EECR } = this.config;
 
     if (this.writeEnabledCycles && this.cpu.cycles > this.writeEnabledCycles) {
       this.cpu.data[EECR] &= ~EEMPE;
     }
     if (this.writeCompleteCycles && this.cpu.cycles > this.writeCompleteCycles) {
-      this.cpu.data[EECR] &= ~EEPE;
-      if (this.cpu.interruptsEnabled && this.cpu.data[EECR] & EERIE) {
-        avrInterrupt(this.cpu, eepromReadyInterrupt);
-      }
+      this.cpu.setInterruptFlag(this.EER);
     }
   }
 }

src/peripherals/spi.spec.ts

@@ -177,6 +177,7 @@ describe('SPI', () => {
     cpu.writeData(SPCR, SPE | MSTR);
     cpu.writeData(SPDR, 0x50);
     spi.tick();
+    cpu.tick();
     expect(cpu.readData(SPSR) & WCOL).toEqual(0);
 
     cpu.writeData(SPDR, 0x51);
@@ -194,11 +195,13 @@ describe('SPI', () => {
     // At this point, write shouldn't be complete yet
     cpu.cycles += 10;
     spi.tick();
+    cpu.tick();
     expect(cpu.pc).toEqual(0);
 
     // 100 cycles later, it should (8 bits * 8 cycles per bit = 64).
     cpu.cycles += 100;
     spi.tick();
+    cpu.tick();
     expect(cpu.data[SPSR] & SPIF).toEqual(0);
     expect(cpu.pc).toEqual(0x22); // SPI Ready interrupt
   });
@@ -213,10 +216,12 @@ describe('SPI', () => {
 
     cpu.cycles = 10;
     spi.tick();
+    cpu.tick();
     expect(cpu.readData(SPDR)).toEqual(0);
 
     cpu.cycles = 32; // 4 cycles per bit * 8 bits = 32
     spi.tick();
+    cpu.tick();
     expect(cpu.readData(SPDR)).toEqual(0x88);
   });
 });

src/peripherals/spi.ts

@@ -1,6 +1,5 @@
-import { CPU } from '../cpu/cpu';
+import { AVRInterruptConfig, CPU } from '../cpu/cpu';
 import { u8 } from '../types';
-import { avrInterrupt } from '../cpu/interrupt';
 
 export interface SPIConfig {
   spiInterrupt: u8;
@@ -42,6 +41,15 @@ export class AVRSPI {
   private transmissionCompleteCycles = 0;
   private receivedByte: u8 = 0;
 
+  // Interrupts
+  private SPI: AVRInterruptConfig = {
+    address: this.config.spiInterrupt,
+    flagRegister: this.config.SPSR,
+    flagMask: SPSR_SPIF,
+    enableRegister: this.config.SPCR,
+    enableMask: SPCR_SPIE,
+  };
+
   constructor(private cpu: CPU, private config: SPIConfig, private freqMHz: number) {
     const { SPCR, SPSR, SPDR } = config;
     cpu.writeHooks[SPDR] = (value: u8) => {
@@ -57,28 +65,26 @@ export class AVRSPI {
       }
 
       // Clear write collision / interrupt flags
-      cpu.data[SPSR] &= ~SPSR_WCOL & ~SPSR_SPIF;
+      cpu.data[SPSR] &= ~SPSR_WCOL;
+      this.cpu.clearInterrupt(this.SPI);
 
       this.receivedByte = this.onTransfer?.(value) ?? 0;
       this.transmissionCompleteCycles = this.cpu.cycles + this.clockDivider * bitsPerByte;
       return true;
     };
+    cpu.writeHooks[SPSR] = (value: u8) => {
+      this.cpu.data[SPSR] = value;
+      this.cpu.clearInterruptByFlag(this.SPI, value);
+    };
   }
 
   tick() {
     if (this.transmissionCompleteCycles && this.cpu.cycles >= this.transmissionCompleteCycles) {
-      const { SPSR, SPDR } = this.config;
-      this.cpu.data[SPSR] |= SPSR_SPIF;
+      const { SPDR } = this.config;
       this.cpu.data[SPDR] = this.receivedByte;
+      this.cpu.setInterruptFlag(this.SPI);
       this.transmissionCompleteCycles = 0;
     }
-    if (this.cpu.interruptsEnabled) {
-      const { SPSR, SPCR, spiInterrupt } = this.config;
-      if (this.cpu.data[SPCR] & SPCR_SPIE && this.cpu.data[SPSR] & SPSR_SPIF) {
-        avrInterrupt(this.cpu, spiInterrupt);
-        this.cpu.data[SPSR] &= ~SPSR_SPIF;
-      }
-    }
   }
 
   get isMaster() {