11/**
22 * AVR-8 Instruction Simulation
33 * Part of AVR8js
4+ *
45 * Reference: http://ww1.microchip.com/downloads/en/devicedoc/atmel-0856-avr-instruction-set-manual.pdf
56 *
6- * Copyright (C) 2019, Uri Shaked
7+ * Instruction timing is currently based on ATmega328p (see the Instruction Set Summary at the end of
8+ * the datasheet)
9+ *
10+ * Copyright (C) 2019, 2020 Uri Shaked
711 */
812
913import { ICPU } from './cpu' ;
@@ -350,6 +354,7 @@ export function avrInstruction(cpu: ICPU) {
350354 } else if ( ( opcode & 0xfe0f ) === 0x900c ) {
351355 /* LDX, 1001 000d dddd 1100 */
352356 cpu . data [ ( opcode & 0x1f0 ) >> 4 ] = cpu . readData ( cpu . dataView . getUint16 ( 26 , true ) ) ;
357+ cpu . cycles ++ ;
353358 } else if ( ( opcode & 0xfe0f ) === 0x900d ) {
354359 /* LDX(INC), 1001 000d dddd 1101 */
355360 const x = cpu . dataView . getUint16 ( 26 , true ) ;
@@ -361,10 +366,11 @@ export function avrInstruction(cpu: ICPU) {
361366 const x = cpu . dataView . getUint16 ( 26 , true ) - 1 ;
362367 cpu . dataView . setUint16 ( 26 , x , true ) ;
363368 cpu . data [ ( opcode & 0x1f0 ) >> 4 ] = cpu . readData ( x ) ;
364- cpu . cycles += 2 ;
369+ cpu . cycles ++ ;
365370 } else if ( ( opcode & 0xfe0f ) === 0x8008 ) {
366371 /* LDY, 1000 000d dddd 1000 */
367372 cpu . data [ ( opcode & 0x1f0 ) >> 4 ] = cpu . readData ( cpu . dataView . getUint16 ( 28 , true ) ) ;
373+ cpu . cycles ++ ;
368374 } else if ( ( opcode & 0xfe0f ) === 0x9009 ) {
369375 /* LDY(INC), 1001 000d dddd 1001 */
370376 const y = cpu . dataView . getUint16 ( 28 , true ) ;
@@ -376,7 +382,7 @@ export function avrInstruction(cpu: ICPU) {
376382 const y = cpu . dataView . getUint16 ( 28 , true ) - 1 ;
377383 cpu . dataView . setUint16 ( 28 , y , true ) ;
378384 cpu . data [ ( opcode & 0x1f0 ) >> 4 ] = cpu . readData ( y ) ;
379- cpu . cycles += 2 ;
385+ cpu . cycles ++ ;
380386 } else if (
381387 ( opcode & 0xd208 ) === 0x8008 &&
382388 ( opcode & 7 ) | ( ( opcode & 0xc00 ) >> 7 ) | ( ( opcode & 0x2000 ) >> 8 )
@@ -386,10 +392,11 @@ export function avrInstruction(cpu: ICPU) {
386392 cpu . dataView . getUint16 ( 28 , true ) +
387393 ( ( opcode & 7 ) | ( ( opcode & 0xc00 ) >> 7 ) | ( ( opcode & 0x2000 ) >> 8 ) )
388394 ) ;
389- cpu . cycles += 2 ;
395+ cpu . cycles ++ ;
390396 } else if ( ( opcode & 0xfe0f ) === 0x8000 ) {
391397 /* LDZ, 1000 000d dddd 0000 */
392398 cpu . data [ ( opcode & 0x1f0 ) >> 4 ] = cpu . readData ( cpu . dataView . getUint16 ( 30 , true ) ) ;
399+ cpu . cycles ++ ;
393400 } else if ( ( opcode & 0xfe0f ) === 0x9001 ) {
394401 /* LDZ(INC), 1001 000d dddd 0001 */
395402 const z = cpu . dataView . getUint16 ( 30 , true ) ;
@@ -401,7 +408,7 @@ export function avrInstruction(cpu: ICPU) {
401408 const z = cpu . dataView . getUint16 ( 30 , true ) - 1 ;
402409 cpu . dataView . setUint16 ( 30 , z , true ) ;
403410 cpu . data [ ( opcode & 0x1f0 ) >> 4 ] = cpu . readData ( z ) ;
404- cpu . cycles += 2 ;
411+ cpu . cycles ++ ;
405412 } else if (
406413 ( opcode & 0xd208 ) === 0x8000 &&
407414 ( opcode & 7 ) | ( ( opcode & 0xc00 ) >> 7 ) | ( ( opcode & 0x2000 ) >> 8 )
@@ -411,7 +418,7 @@ export function avrInstruction(cpu: ICPU) {
411418 cpu . dataView . getUint16 ( 30 , true ) +
412419 ( ( opcode & 7 ) | ( ( opcode & 0xc00 ) >> 7 ) | ( ( opcode & 0x2000 ) >> 8 ) )
413420 ) ;
414- cpu . cycles += 2 ;
421+ cpu . cycles ++ ;
415422 } else if ( opcode === 0x95c8 ) {
416423 /* LPM, 1001 0101 1100 1000 */
417424 cpu . data [ 0 ] = cpu . progBytes [ cpu . dataView . getUint16 ( 30 , true ) ] ;
@@ -666,11 +673,13 @@ export function avrInstruction(cpu: ICPU) {
666673 } else if ( ( opcode & 0xfe0f ) === 0x920c ) {
667674 /* STX, 1001 001r rrrr 1100 */
668675 cpu . writeData ( cpu . dataView . getUint16 ( 26 , true ) , cpu . data [ ( opcode & 0x1f0 ) >> 4 ] ) ;
676+ cpu . cycles ++ ;
669677 } else if ( ( opcode & 0xfe0f ) === 0x920d ) {
670678 /* STX(INC), 1001 001r rrrr 1101 */
671679 const x = cpu . dataView . getUint16 ( 26 , true ) ;
672680 cpu . writeData ( x , cpu . data [ ( opcode & 0x1f0 ) >> 4 ] ) ;
673681 cpu . dataView . setUint16 ( 26 , x + 1 , true ) ;
682+ cpu . cycles ++ ;
674683 } else if ( ( opcode & 0xfe0f ) === 0x920e ) {
675684 /* STX(DEC), 1001 001r rrrr 1110 */
676685 const i = cpu . data [ ( opcode & 0x1f0 ) >> 4 ] ;
@@ -681,12 +690,14 @@ export function avrInstruction(cpu: ICPU) {
681690 } else if ( ( opcode & 0xfe0f ) === 0x8208 ) {
682691 /* STY, 1000 001r rrrr 1000 */
683692 cpu . writeData ( cpu . dataView . getUint16 ( 28 , true ) , cpu . data [ ( opcode & 0x1f0 ) >> 4 ] ) ;
693+ cpu . cycles ++ ;
684694 } else if ( ( opcode & 0xfe0f ) === 0x9209 ) {
685695 /* STY(INC), 1001 001r rrrr 1001 */
686696 const i = cpu . data [ ( opcode & 0x1f0 ) >> 4 ] ;
687697 const y = cpu . dataView . getUint16 ( 28 , true ) ;
688698 cpu . writeData ( y , i ) ;
689699 cpu . dataView . setUint16 ( 28 , y + 1 , true ) ;
700+ cpu . cycles ++ ;
690701 } else if ( ( opcode & 0xfe0f ) === 0x920a ) {
691702 /* STY(DEC), 1001 001r rrrr 1010 */
692703 const i = cpu . data [ ( opcode & 0x1f0 ) >> 4 ] ;
@@ -708,11 +719,13 @@ export function avrInstruction(cpu: ICPU) {
708719 } else if ( ( opcode & 0xfe0f ) === 0x8200 ) {
709720 /* STZ, 1000 001r rrrr 0000 */
710721 cpu . writeData ( cpu . dataView . getUint16 ( 30 , true ) , cpu . data [ ( opcode & 0x1f0 ) >> 4 ] ) ;
722+ cpu . cycles ++ ;
711723 } else if ( ( opcode & 0xfe0f ) === 0x9201 ) {
712724 /* STZ(INC), 1001 001r rrrr 0001 */
713725 const z = cpu . dataView . getUint16 ( 30 , true ) ;
714726 cpu . writeData ( z , cpu . data [ ( opcode & 0x1f0 ) >> 4 ] ) ;
715727 cpu . dataView . setUint16 ( 30 , z + 1 , true ) ;
728+ cpu . cycles ++ ;
716729 } else if ( ( opcode & 0xfe0f ) === 0x9202 ) {
717730 /* STZ(DEC), 1001 001r rrrr 0010 */
718731 const i = cpu . data [ ( opcode & 0x1f0 ) >> 4 ] ;
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