Initial support for STM32H5, sunny day boot

STM32H5: Tested sunny day boot

- Temporarily decreased clock speed to 125MHz
- Test app working
- Re-mapped Nucleo board LEDs
- Tested on STM32H563ZI

Author: danielinux

arch.mk

@@ -164,6 +164,21 @@ ifeq ($(ARCH),ARM)
     SPI_TARGET=stm32
   endif
 
+  ifeq ($(TARGET),stm32h5)
+    CORTEX_M33=1
+    CFLAGS+=-Ihal
+    ARCH_FLASH_OFFSET=0x08000000
+    ifeq ($(TZEN),1)
+      WOLFBOOT_ORIGIN=0x0C000000
+    else
+      WOLFBOOT_ORIGIN=0x08000000
+    endif
+    ifneq ($(TZEN),1)
+      LSCRIPT_IN=hal/$(TARGET)-ns.ld
+    endif
+    SPI_TARGET=stm32
+  endif
+
   ## Cortex-M CPU
 ifeq ($(CORTEX_M33),1)
   CFLAGS+=-mcpu=cortex-m33 -DCORTEX_M33

config/examples/stm32h5-nonsecure-dualbank.config

@@ -0,0 +1,27 @@
+ARCH?=ARM
+TZEN?=0
+TARGET?=stm32h5
+SIGN?=ECC256
+HASH?=SHA256
+DEBUG?=1
+VTOR?=1
+CORTEX_M0?=0
+CORTEX_M33?=1
+NO_ASM?=0
+NO_MPU=1
+EXT_FLASH?=0
+SPI_FLASH?=0
+ALLOW_DOWNGRADE?=0
+NVM_FLASH_WRITEONCE?=1
+WOLFBOOT_VERSION?=1
+V?=0
+SPMATH?=1
+RAM_CODE?=0
+DUALBANK_SWAP?=1
+WOLFBOOT_PARTITION_SIZE?=0x20000
+WOLFBOOT_SECTOR_SIZE?=0x2000
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08100000
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x817F000
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x81FE000
+FLAGS_HOME=0
+DISABLE_BACKUP=0

config/examples/stm32h5.config

@@ -0,0 +1,27 @@
+ARCH?=ARM
+TZEN?=0
+TARGET?=stm32h5
+SIGN?=ECC256
+HASH?=SHA256
+DEBUG?=1
+VTOR?=1
+CORTEX_M0?=0
+CORTEX_M33?=1
+NO_ASM?=0
+NO_MPU=1
+EXT_FLASH?=0
+SPI_FLASH?=0
+ALLOW_DOWNGRADE?=0
+NVM_FLASH_WRITEONCE?=1
+WOLFBOOT_VERSION?=1
+V?=0
+SPMATH?=1
+RAM_CODE?=0
+DUALBANK_SWAP?=0
+WOLFBOOT_PARTITION_SIZE?=0x20000
+WOLFBOOT_SECTOR_SIZE?=0x2000
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08100000
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x817F000
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x81FE000
+FLAGS_HOME=0
+DISABLE_BACKUP=0

hal/stm32_tz.c

@@ -29,6 +29,10 @@
     #include "hal/stm32u5.h"
 #endif
 
+#ifdef PLATFORM_stm32h5
+    #include "hal/stm32h5.h"
+#endif
+
 #include "image.h"
 #include "hal.h"
 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (!defined(FLAGS_HOME) || !defined(DISABLE_BACKUP))
@@ -81,15 +85,25 @@ void hal_tz_claim_nonsecure_area(uint32_t address, int len)
         hal_flash_wait_complete(0);
         hal_flash_nonsecure_lock();
         /* Erase claimed non-secure page, in secure mode */
+#ifndef PLATFORM_stm32h5
         reg = FLASH_CR & (~((FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER | FLASH_CR_BKER | FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_MER2));
-        FLASH_CR = reg | ((page_n << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER | FLASH_CR_BKER);
+        FLASH_CR = reg | ((page_n << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER);
+#else
+        reg = FLASH_CR & (~((FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT) | FLASH_CR_SER | FLASH_CR_BER | FLASH_CR_PG | FLASH_CR_MER));
+        FLASH_CR = reg | ((page_n << FLASH_CR_PNB_SHIFT) | FLASH_CR_SER);
+#endif
+
         DMB();
         FLASH_CR |= FLASH_CR_STRT;
         ISB();
         hal_flash_wait_complete(0);
         address += FLASH_PAGE_SIZE;
     }
+#ifndef PLATFORM_stm32h5
     FLASH_CR &= ~FLASH_CR_PER ;
+#else
+    FLASH_CR &= ~FLASH_CR_SER ;
+#endif
 }
 #else
 #define claim_nonsecure_area(...) do{}while(0)

hal/stm32h5-ns.ld

@@ -0,0 +1,50 @@
+MEMORY
+{
+    FLASH (rx) : ORIGIN = 0x08000000, LENGTH = @BOOTLOADER_PARTITION_SIZE@
+    RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* mapping TCM only */
+}
+
+SECTIONS
+{
+    .text :
+    {
+        _start_text = .;
+        KEEP(*(.isr_vector))
+        *(.text*)
+        *(.rodata*)
+        . = ALIGN(4);
+        _end_text = .;
+    } > FLASH
+
+    .edidx :
+    {
+        . = ALIGN(4);
+        *(.ARM.exidx*)
+    } > FLASH
+
+    _stored_data = .;
+    .data : AT (_stored_data)
+    {
+        _start_data = .;
+        KEEP(*(.data*))
+        . = ALIGN(4);
+        KEEP(*(.ramcode))
+        . = ALIGN(4);
+        _end_data = .;
+    } > RAM
+
+    .bss (NOLOAD) :
+    {
+        _start_bss = .;
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        _end_bss = .;
+        __bss_end__ = .;
+        _end = .;
+    } > RAM
+    . = ALIGN(4);
+}
+
+END_STACK = ORIGIN(RAM) + LENGTH(RAM);