7070#define GPIO_CLOCK_ER_VAL (1 << 1)
7171#define GPIOB_BASE 0x40020400
7272#define GPIO_MODE (*(volatile uint32_t *)(GPIOB_BASE + 0x00))
73- #define GPIO_AF (*(volatile uint32_t *)(GPIOB_BASE + 0x20))
73+ #define GPIO_AFL (*(volatile uint32_t *)(GPIOB_BASE + 0x20))
74+ #define GPIO_AFH (*(volatile uint32_t *)(GPIOB_BASE + 0x24))
7475#endif
7576
7677/* UART3 Config */
9293#define GPIO_CLOCK_ER_VAL (1 << 3)
9394#define GPIOD_BASE 0x40020c00
9495#define GPIO_MODE (*(volatile uint32_t *)(GPIOD_BASE + 0x00))
95- #define GPIO_AF (*(volatile uint32_t *)(GPIOD_BASE + 0x20))
96+ #define GPIO_AFL (*(volatile uint32_t *)(GPIOD_BASE + 0x20))
97+ #define GPIO_AFH (*(volatile uint32_t *)(GPIOD_BASE + 0x24))
9698#endif
9799
98100
@@ -106,10 +108,29 @@ static void uart_pins_setup(void)
106108 reg = GPIO_MODE & ~ (0x03 << (UART_TX_PIN * 2 ));
107109 GPIO_MODE = reg | (2 << (UART_TX_PIN * 2 ));
108110
109- reg = GPIO_AF & ~(0xf << (UART_TX_PIN * 4 ));
110- GPIO_AF = reg | (UART_PIN_AF << (UART_TX_PIN * 4 ));
111- reg = GPIO_AF & ~(0xf << (UART_RX_PIN * 4 ));
112- GPIO_AF = reg | (UART_PIN_AF << (UART_RX_PIN * 4 ));
111+ /* The alternate function register is split across two 32bit
112+ * registers (AFL, AFH). AFL covers pins 0 through 7, and
113+ * AFH covers pins 8 through 15. The code below determines
114+ * which register to use at compile time based on the chosen
115+ * pin number
116+ */
117+
118+ #if UART_TX_PIN > 7
119+ reg = GPIO_AFH & ~(0xf << ((UART_TX_PIN - 8 ) * 4 ));
120+ GPIO_AFH = reg | (UART_PIN_AF << ((UART_TX_PIN - 8 ) * 4 ));
121+ #else
122+ reg = GPIO_AFL & ~(0xf << (UART_TX_PIN * 4 ));
123+ GPIO_AFL = reg | (UART_PIN_AF << (UART_TX_PIN * 4 ));
124+ #endif
125+
126+ #if UART_RX_PIN > 7
127+ reg = GPIO_AFH & ~(0xf << ((UART_RX_PIN - 8 ) * 4 ));
128+ GPIO_AFH = reg | (UART_PIN_AF << ((UART_RX_PIN - 8 ) * 4 ));
129+ #else
130+ reg = GPIO_AFL & ~(0xf << (UART_RX_PIN * 4 ));
131+ GPIO_AFL = reg | (UART_PIN_AF << (UART_RX_PIN * 4 ));
132+ #endif
133+
113134}
114135
115136int uart_tx (const uint8_t c )
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