Fixes for getting the "test-app" booting

Author: dgarske

config/examples/versal_vmk180.config

@@ -27,6 +27,10 @@ DEBUG?=1
 DEBUG_SYMBOLS=1
 DEBUG_UART=1
 
+# Boot Benchmarking (optional):
+# Enables timing of boot operations (flash read, integrity, signature).
+BOOT_BENCHMARK?=1
+
 VTOR?=1
 CORTEX_M0?=0
 NO_ASM?=0

docs/Targets.md

@@ -1862,7 +1862,7 @@ qemu-system-aarch64 -machine xlnx-zcu102 -cpu cortex-a53 -serial stdio -display
 
 ## Versal Gen 1 VMK180
 
-AMD Versal Prime VM1802 ACAP - Dual ARM Cortex-A72 (VMK180 Evaluation Board)
+AMD Versal Prime Series VMK180 Evaluation Kit - Versal Prime XCVM1802-2MSEVSVA2197 Adaptive SoC - Dual ARM Cortex-A72
 
 wolfBoot replaces U-Boot in the Versal boot flow:
 ```
@@ -1961,6 +1961,29 @@ Flash `BOOT.BIN` to QSPI flash using one of the following methods:
   sf write ${loadaddr} 0 ${filesize}
   ```
 
+### QSPI Flash
+
+VMK180 uses dual parallel MT25QU01GBBB flash (128MB each, 256MB total). The QSPI driver supports:
+- DMA mode (default) or IO polling mode (`GQSPI_MODE_IO`)
+- Quad SPI (4-bit) for faster reads
+- 4-byte addressing for full flash access
+- Hardware striping for dual parallel operation
+- 75MHz default clock (configurable via `GQSPI_CLK_DIV`)
+
+### Building and Signing Test Application
+
+```sh
+# Build and sign the test application
+make test-app/image.bin
+make test-app/image_v1_signed.bin
+```
+
+The signed test application will be at `test-app/image_v1_signed.bin`.
+
+### Flashing Test Application
+
+After flashing `BOOT.BIN` to QSPI offset 0x0, flash the signed test app to the boot partition at offset `0x800000` using your preferred method.
+
 ### Example Boot Output
 
 ```
@@ -1969,11 +1992,30 @@ wolfBoot Secure Boot - AMD Versal
 ========================================
 Current EL: 2
 Timer Freq: 99999904 Hz
-ext_flash_read: STUB
-ext_flash_read: STUB
-Versions: Boot 0, Update 0
-No valid image found!
-wolfBoot: PANIC!
+QSPI: Lower ID: 20 BB 21
+QSPI: Upper ID: 20 BB 21
+QSPI: 75MHz, Quad mode, DMA
+Versions: Boot 1, Update 0
+Trying Boot partition at 0x800000
+Loading header 512 bytes from 0x800000 to 0xFFFFE00
+Loading image 664 bytes from 0x800200 to 0x10000000...done
+Boot partition: 0xFFFFE00 (sz 664, ver 0x1, type 0x601)
+Checking integrity...done
+Verifying signature...done
+Successfully selected image in part: 0
+Firmware Valid
+Loading elf at 0x10000000
+Invalid elf, falling back to raw binary
+Loading DTB (size 24894) from 0x1000 to RAM at 0x1000
+Booting at 0x10000000
+
+===========================================
+ wolfBoot Test Application - AMD Versal
+===========================================
+
+Application running successfully!
+
+Entering idle loop...
 ```
 
 

hal/versal.c

@@ -272,6 +272,21 @@ void hal_delay_us(uint32_t us)
         ;
 }
 
+/**
+ * Get current time in microseconds (for benchmarking)
+ */
+uint64_t hal_get_timer_us(void)
+{
+    uint64_t cntpct = timer_get_count();
+    uint64_t cntfrq = timer_get_freq();
+
+    if (cntfrq == 0)
+        cntfrq = TIMER_CLK_FREQ;
+
+    /* Convert to microseconds: (count * 1000000) / freq */
+    return (cntpct * 1000000ULL) / cntfrq;
+}
+
 
 /* ============================================================================
  * QSPI Flash Driver (GQSPI)
@@ -473,7 +488,9 @@ static void flush_dcache_range(uintptr_t start, uintptr_t end)
     __asm__ volatile("dsb sy" : : : "memory");
 }
 
-/* Wait for DMA completion */
+/* Wait for DMA completion
+ * Returns: 0 on success, -1 on timeout
+ */
 static int qspi_dma_wait(void)
 {
     uint32_t timeout = GQSPIDMA_TIMEOUT_TRIES;
@@ -483,6 +500,8 @@ static int qspi_dma_wait(void)
 
     if (timeout == 0) {
         QSPI_DEBUG_PRINTF("QSPI: DMA timeout\n");
+        /* Clear any pending interrupts */
+        GQSPIDMA_ISR = GQSPIDMA_ISR_ALL_MASK;
         return -1;
     }
 
@@ -782,10 +801,12 @@ static int qspi_transfer_qread_dma(QspiDev_t *dev, const uint8_t *cmd, uint32_t
 
     /* DMA RX Phase */
     if (ret == 0 && rxLen > 0) {
-        uint32_t remaining = rxLen;
+        uint32_t remaining;
         uint32_t xferSz;
 
-        /* Check alignment - DMA requires cache-line aligned buffer */
+        /* Check alignment - DMA requires cache-line aligned buffer.
+         * If unaligned or not a multiple of 4 bytes, use temp buffer.
+         * CRITICAL: GenFIFO transfer size must match DMA size! */
         if (((uintptr_t)rxData & (GQSPI_DMA_ALIGN - 1)) || (rxLen & 3)) {
             /* Use temp buffer for unaligned data */
             dmaPtr = dma_tmpbuf;
@@ -799,6 +820,9 @@ static int qspi_transfer_qread_dma(QspiDev_t *dev, const uint8_t *cmd, uint32_t
             dmaLen = rxLen;
         }
 
+        /* GenFIFO must request the same number of bytes as DMA expects */
+        remaining = dmaLen;
+
         /* Setup DMA destination */
         GQSPIDMA_DST = ((uintptr_t)dmaPtr & 0xFFFFFFFFUL);
         GQSPIDMA_DST_MSB = ((uintptr_t)dmaPtr >> 32);
@@ -839,7 +863,7 @@ static int qspi_transfer_qread_dma(QspiDev_t *dev, const uint8_t *cmd, uint32_t
         /* Invalidate cache after DMA */
         flush_dcache_range((uintptr_t)dmaPtr, (uintptr_t)dmaPtr + dmaLen);
 
-        /* Copy from temp buffer if needed */
+        /* Copy from temp buffer if needed (only copy requested bytes) */
         if (ret == 0 && useTemp) {
             memcpy(rxData, dmaPtr, rxLen);
         }
@@ -1224,11 +1248,12 @@ static void qspi_init(void)
     GQSPI_ISR = GQSPI_IXR_ALL_MASK;
     dsb();
 
-    /* Preserve PLM's CFG but switch to IO mode for our transfers
+    /* Preserve PLM's CFG but set IO mode for initial commands (ID read, etc.)
      * PLM: 0xA0080010 = DMA mode | manual start | WP_HOLD | CLK_POL
-     * Key: Keep manual start mode (bit 29) and clock settings */
+     * Key: Keep manual start mode (bit 29) and clock settings
+     * Note: qspi_transfer_qread_dma() will switch to DMA mode for reads */
     cfg = (cfg & ~GQSPI_CFG_MODE_EN_MASK);  /* Clear mode bits */
-    cfg |= GQSPI_CFG_MODE_EN_IO;            /* Set IO mode */
+    cfg |= GQSPI_CFG_MODE_EN_IO;            /* Set IO mode for init */
     GQSPI_CFG = cfg;
     dsb();
 
@@ -1237,6 +1262,18 @@ static void qspi_init(void)
     GQSPI_RX_THRESH = 1;
     GQSPI_GF_THRESH = 16;
 
+#ifndef GQSPI_MODE_IO
+    /* Initialize DMA controller - this was missing compared to zynq.c!
+     * Without this, DMA transfers can hang or timeout because the DMA
+     * controller is in an undefined state after PLM handoff.
+     */
+    GQSPIDMA_CTRL = GQSPIDMA_CTRL_DEF;
+    GQSPIDMA_CTRL2 = GQSPIDMA_CTRL2_DEF;
+    GQSPIDMA_ISR = GQSPIDMA_ISR_ALL_MASK;  /* Clear all pending interrupts */
+    GQSPIDMA_IER = GQSPIDMA_ISR_ALL_MASK;  /* Enable all interrupts */
+    dsb();
+#endif
+
     QSPI_DEBUG_PRINTF("QSPI: After config - CFG=0x%08x\n", GQSPI_CFG);
 
     /* Configure device for single flash (lower) first */
@@ -1353,9 +1390,35 @@ void hal_prepare_boot(void)
     }
 #endif
 
-    /* Memory barriers before jumping to application */
-    dsb();
-    isb();
+    /* Clean and invalidate caches for the loaded application.
+     * The application was written to RAM via D-cache, but the CPU will
+     * fetch instructions via I-cache from main memory. We must:
+     * 1. Clean D-cache (flush dirty data to memory)
+     * 2. Invalidate I-cache (ensure fresh instruction fetch)
+     */
+
+    /* Clean entire D-cache to Point of Coherency */
+    __asm__ volatile("dsb sy");
+
+    /* Clean D-cache for application region (0x10000000, 1MB should be enough) */
+    {
+        uintptr_t addr;
+        uintptr_t end = 0x10000000 + (1 * 1024 * 1024);
+        for (addr = 0x10000000; addr < end; addr += 64) {
+            /* DC CVAC - Clean data cache line by VA to PoC */
+            __asm__ volatile("dc cvac, %0" : : "r"(addr));
+        }
+    }
+
+    /* Data synchronization barrier - ensure clean completes */
+    __asm__ volatile("dsb sy");
+
+    /* Invalidate instruction cache to ensure fresh code is fetched */
+    __asm__ volatile("ic iallu");
+
+    /* Ensure cache invalidation completes before jumping */
+    __asm__ volatile("dsb sy");
+    __asm__ volatile("isb");
 }
 
 #ifdef MMU
@@ -1504,9 +1567,14 @@ int ext_flash_read(uintptr_t address, uint8_t *data, int len)
         return -1;
     }
 
+    QSPI_DEBUG_PRINTF("ext_flash_read: addr=0x%lx len=%d\n",
+                      (unsigned long)address, len);
+
     if (qspiDev.stripe) {
         /* For dual parallel the address is divided by 2 */
         addr /= 2;
+        QSPI_DEBUG_PRINTF("  stripe mode: flash_addr=0x%lx\n",
+                          (unsigned long)addr);
     }
 
     /* Use Quad Read command (0x6C) with 4-byte address */
@@ -1523,7 +1591,22 @@ int ext_flash_read(uintptr_t address, uint8_t *data, int len)
     ret = qspi_transfer_qread_dma(&qspiDev, cmd, 5, data, len, GQSPI_DUMMY_READ);
 #endif
 
-    return ret;
+    /* On DMA timeout, fill buffer with 0xFF to simulate unwritten flash.
+     * This handles reads to partition trailer areas that haven't been written.
+     * wolfBoot will see 0xFF (not magic) and handle appropriately. */
+    if (ret != 0) {
+        memset(data, 0xFF, len);
+    }
+
+    QSPI_DEBUG_PRINTF("ext_flash_read: ret=%d data[0-7]=%02x %02x %02x %02x %02x %02x %02x %02x\n",
+                      ret,
+                      len > 0 ? data[0] : 0, len > 1 ? data[1] : 0,
+                      len > 2 ? data[2] : 0, len > 3 ? data[3] : 0,
+                      len > 4 ? data[4] : 0, len > 5 ? data[5] : 0,
+                      len > 6 ? data[6] : 0, len > 7 ? data[7] : 0);
+
+    /* Return bytes read on success (like zynq.c) */
+    return (ret == 0) ? len : ret;
 }
 
 int ext_flash_erase(uintptr_t address, int len)

hal/versal.h

@@ -61,6 +61,21 @@
 
 #endif /* USE_BUILTIN_STARTUP */
 
+/* ============================================================================
+ * Versal-specific Boot Defaults
+ * ============================================================================
+ * SKIP_GIC_INIT: Versal uses GICv3 (not GICv2 like ZynqMP).
+ *                BL31 handles GIC initialization, so skip gicv2_init_secure().
+ * BOOT_EL1:      wolfBoot runs at EL2, but applications (Linux, test-app)
+ *                expect EL1. Transition from EL2 to EL1 before jumping to app.
+ */
+#ifndef SKIP_GIC_INIT
+#define SKIP_GIC_INIT 1
+#endif
+#ifndef BOOT_EL1
+#define BOOT_EL1 1
+#endif
+
 
 /* ============================================================================
  * Memory Map

include/hal.h

@@ -53,8 +53,8 @@ void hal_deinit();
 
 void hal_init(void);
 
-#ifdef WOLFBOOT_UPDATE_DISK
-/* Timer functions (platform-specific) */
+/* Timer functions (platform-specific, used for benchmarking) */
+#if defined(WOLFBOOT_UPDATE_DISK) || defined(BOOT_BENCHMARK)
 uint64_t hal_get_timer_us(void);
 #endif
 

options.mk

@@ -604,6 +604,15 @@ endif
 ifeq ($(NO_QNX),1)
   CFLAGS+=-D"NO_QNX"
 endif
+ifeq ($(SKIP_GIC_INIT),1)
+  CFLAGS+=-D"SKIP_GIC_INIT"
+endif
+ifeq ($(BOOT_EL1),1)
+  CFLAGS+=-D"BOOT_EL1"
+endif
+ifeq ($(BOOT_BENCHMARK),1)
+  CFLAGS+=-D"BOOT_BENCHMARK"
+endif
 
 ifeq ($(ALLOW_DOWNGRADE),1)
   CFLAGS+= -D"ALLOW_DOWNGRADE"