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AlexLanzanoAlexLanzano
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Update stm32f4 test-app to use config options to setup clock and uart
Allows the pll clock to be configured using the config macros instead of being hard coded.
1 parent 72baf96 commit 248fd98

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2 files changed

+90
-50
lines changed

2 files changed

+90
-50
lines changed

‎test-app/app_stm32f4.c‎

Lines changed: 77 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -34,14 +34,15 @@
3434

3535
#ifdef TARGET_stm32f4
3636

37-
#define UART1 (0x40011000)
38-
39-
#define UART1_SR (*(volatile uint32_t *)(UART1))
40-
#define UART1_DR (*(volatile uint32_t *)(UART1 + 0x04))
41-
#define UART1_BRR (*(volatile uint32_t *)(UART1 + 0x08))
42-
#define UART1_CR1 (*(volatile uint32_t *)(UART1 + 0x0c))
43-
#define UART1_CR2 (*(volatile uint32_t *)(UART1 + 0x10))
37+
#ifndef CLOCK_SPEED
38+
#define CLOCK_SPEED (168000000)
39+
#endif
4440

41+
/* Common UART Config */
42+
#if !defined(USE_UART1) && !defined(USE_UART3)
43+
#define USE_UART3
44+
#endif
45+
#define UART_PIN_AF 7
4546
#define UART_CR1_UART_ENABLE (1 << 13)
4647
#define UART_CR1_SYMBOL_LEN (1 << 12)
4748
#define UART_CR1_PARITY_ENABLED (1 << 10)
@@ -53,21 +54,52 @@
5354
#define UART_SR_RX_NOTEMPTY (1 << 5)
5455

5556

56-
#define CLOCK_SPEED (168000000)
57+
/* Common GPIO Config */
58+
#define GPIO_MODE_AF (2)
5759

58-
#define APB2_CLOCK_ER (*(volatile uint32_t *)(0x40023844))
59-
#define UART1_APB2_CLOCK_ER (1 << 4)
60+
/* UART1 Config */
61+
#ifdef USE_UART1
62+
#define UART_RX_PIN 7
63+
#define UART_TX_PIN 6
6064

61-
#define AHB1_CLOCK_ER (*(volatile uint32_t *)(0x40023830))
62-
#define GPIOB_AHB1_CLOCK_ER (1 << 1)
65+
#define UART1 (0x40011000)
66+
#define UART_SR (*(volatile uint32_t *)(UART1))
67+
#define UART_DR (*(volatile uint32_t *)(UART1 + 0x04))
68+
#define UART_BRR (*(volatile uint32_t *)(UART1 + 0x08))
69+
#define UART_CR1 (*(volatile uint32_t *)(UART1 + 0x0c))
70+
#define UART_CR2 (*(volatile uint32_t *)(UART1 + 0x10))
71+
72+
#define UART_CLOCK_ER (*(volatile uint32_t *)(0x40023844))
73+
#define UART_CLOCK_ER_VAL (1 << 4)
74+
75+
#define GPIO_CLOCK_ER (*(volatile uint32_t *)(0x40023830))
76+
#define GPIO_CLOCK_ER_VAL (1 << 1)
6377
#define GPIOB_BASE 0x40020400
78+
#define GPIO_MODE (*(volatile uint32_t *)(GPIOB_BASE + 0x00))
79+
#define GPIO_AF (*(volatile uint32_t *)(GPIOB_BASE + 0x20))
80+
#endif
6481

65-
#define GPIOB_MODE (*(volatile uint32_t *)(GPIOB_BASE + 0x00))
66-
#define GPIOB_AFL (*(volatile uint32_t *)(GPIOB_BASE + 0x20))
67-
#define GPIOB_AFH (*(volatile uint32_t *)(GPIOB_BASE + 0x24))
68-
#define UART1_PIN_AF 7
69-
#define UART1_RX_PIN 7
70-
#define UART1_TX_PIN 6
82+
/* UART3 Config */
83+
#ifdef USE_UART3
84+
#define UART_RX_PIN 9
85+
#define UART_TX_PIN 8
86+
87+
#define UART3 (0x40004800)
88+
#define UART_SR (*(volatile uint32_t *)(UART3))
89+
#define UART_DR (*(volatile uint32_t *)(UART3 + 0x04))
90+
#define UART_BRR (*(volatile uint32_t *)(UART3 + 0x08))
91+
#define UART_CR1 (*(volatile uint32_t *)(UART3 + 0x0c))
92+
#define UART_CR2 (*(volatile uint32_t *)(UART3 + 0x10))
93+
94+
#define UART_CLOCK_ER (*(volatile uint32_t *)(0x40023840))
95+
#define UART_CLOCK_ER_VAL (1 << 18)
96+
97+
#define GPIO_CLOCK_ER (*(volatile uint32_t *)(0x40023830))
98+
#define GPIO_CLOCK_ER_VAL (1 << 3)
99+
#define GPIOD_BASE 0x40020c00
100+
#define GPIO_MODE (*(volatile uint32_t *)(GPIOD_BASE + 0x00))
101+
#define GPIO_AF (*(volatile uint32_t *)(GPIOD_BASE + 0x20))
102+
#endif
71103

72104
#define MSGSIZE 16
73105
#define PAGESIZE (256)
@@ -100,26 +132,26 @@ void uart_write(const char c)
100132
{
101133
uint32_t reg;
102134
do {
103-
reg = UART1_SR;
135+
reg = UART_SR;
104136
} while ((reg & UART_SR_TX_EMPTY) == 0);
105-
UART1_DR = c;
137+
UART_DR = c;
106138
}
107139

108140
static void uart_pins_setup(void)
109141
{
110142
uint32_t reg;
111-
AHB1_CLOCK_ER |= GPIOB_AHB1_CLOCK_ER;
143+
GPIO_CLOCK_ER |= GPIO_CLOCK_ER_VAL;
112144
/* Set mode = AF */
113-
reg = GPIOB_MODE & ~ (0x03 << (UART1_RX_PIN * 2));
114-
GPIOB_MODE = reg | (2 << (UART1_RX_PIN * 2));
115-
reg = GPIOB_MODE & ~ (0x03 << (UART1_TX_PIN * 2));
116-
GPIOB_MODE = reg | (2 << (UART1_TX_PIN * 2));
145+
reg = GPIO_MODE & ~ (0x03 << (UART_RX_PIN * 2));
146+
GPIO_MODE = reg | (2 << (UART_RX_PIN * 2));
147+
reg = GPIO_MODE & ~ (0x03 << (UART_TX_PIN * 2));
148+
GPIO_MODE = reg | (2 << (UART_TX_PIN * 2));
117149

118150
/* Alternate function: use low pins (6 and 7) */
119-
reg = GPIOB_AFL & ~(0xf << ((UART1_TX_PIN) * 4));
120-
GPIOB_AFL = reg | (UART1_PIN_AF << ((UART1_TX_PIN) * 4));
121-
reg = GPIOB_AFL & ~(0xf << ((UART1_RX_PIN) * 4));
122-
GPIOB_AFL = reg | (UART1_PIN_AF << ((UART1_RX_PIN) * 4));
151+
reg = GPIO_AF & ~(0xf << ((UART_TX_PIN) * 4));
152+
GPIO_AF = reg | (UART_PIN_AF << ((UART_TX_PIN) * 4));
153+
reg = GPIO_AF & ~(0xf << ((UART_RX_PIN) * 4));
154+
GPIO_AF = reg | (UART_PIN_AF << ((UART_RX_PIN) * 4));
123155
}
124156

125157
int uart_setup(uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
@@ -128,40 +160,40 @@ int uart_setup(uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
128160
/* Enable pins and configure for AF7 */
129161
uart_pins_setup();
130162
/* Turn on the device */
131-
APB2_CLOCK_ER |= UART1_APB2_CLOCK_ER;
163+
UART_CLOCK_ER |= UART_CLOCK_ER_VAL;
132164

133165
/* Configure for TX + RX */
134-
UART1_CR1 |= (UART_CR1_TX_ENABLE | UART_CR1_RX_ENABLE);
166+
UART_CR1 |= (UART_CR1_TX_ENABLE | UART_CR1_RX_ENABLE);
135167

136168
/* Configure clock */
137-
UART1_BRR = CLOCK_SPEED / bitrate;
169+
UART_BRR = CLOCK_SPEED / bitrate;
138170

139171
/* Configure data bits */
140172
if (data == 8)
141-
UART1_CR1 &= ~UART_CR1_SYMBOL_LEN;
173+
UART_CR1 &= ~UART_CR1_SYMBOL_LEN;
142174
else
143-
UART1_CR1 |= UART_CR1_SYMBOL_LEN;
175+
UART_CR1 |= UART_CR1_SYMBOL_LEN;
144176

145177
/* Configure parity */
146178
switch (parity) {
147179
case 'O':
148-
UART1_CR1 |= UART_CR1_PARITY_ODD;
180+
UART_CR1 |= UART_CR1_PARITY_ODD;
149181
/* fall through to enable parity */
150182
case 'E':
151-
UART1_CR1 |= UART_CR1_PARITY_ENABLED;
183+
UART_CR1 |= UART_CR1_PARITY_ENABLED;
152184
break;
153185
default:
154-
UART1_CR1 &= ~(UART_CR1_PARITY_ENABLED | UART_CR1_PARITY_ODD);
186+
UART_CR1 &= ~(UART_CR1_PARITY_ENABLED | UART_CR1_PARITY_ODD);
155187
}
156188
/* Set stop bits */
157-
reg = UART1_CR2 & ~UART_CR2_STOPBITS;
189+
reg = UART_CR2 & ~UART_CR2_STOPBITS;
158190
if (stop > 1)
159-
UART1_CR2 = reg & (2 << 12);
191+
UART_CR2 = reg & (2 << 12);
160192
else
161-
UART1_CR2 = reg;
193+
UART_CR2 = reg;
162194

163195
/* Turn on uart */
164-
UART1_CR1 |= UART_CR1_UART_ENABLE;
196+
UART_CR1 |= UART_CR1_UART_ENABLE;
165197

166198
return 0;
167199
}
@@ -171,9 +203,9 @@ char uart_read(void)
171203
char c;
172204
volatile uint32_t reg;
173205
do {
174-
reg = UART1_SR;
206+
reg = UART_SR;
175207
} while ((reg & UART_SR_RX_NOTEMPTY) == 0);
176-
c = (char)(UART1_DR & 0xff);
208+
c = (char)(UART_DR & 0xff);
177209
return c;
178210
}
179211

@@ -215,7 +247,7 @@ void main(void) {
215247
flash_set_waitstates();
216248
clock_config();
217249
led_pwm_setup();
218-
pwm_init(CPU_FREQ, 0);
250+
pwm_init(CLOCK_SPEED, 0);
219251

220252
/* Dim the led by altering the PWM duty-cicle
221253
* in isr_tim2 (timer.c)
@@ -224,7 +256,7 @@ void main(void) {
224256
* to the blue led increases/decreases making a pulse
225257
* effect.
226258
*/
227-
timer_init(CPU_FREQ, 1, 50);
259+
timer_init(CLOCK_SPEED, 1, 50);
228260
uart_setup(115200, 8, 'N', 1);
229261
memset(page, 0xFF, PAGESIZE);
230262
asm volatile ("cpsie i");

‎test-app/system.c‎

Lines changed: 13 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -57,12 +57,20 @@
5757
#define RCC_PRESCALER_DIV_4 9
5858

5959

60-
/* STM32F4-Discovery, 168 MHz */
60+
/* STM32F4 */
6161
#ifdef TARGET_stm32f4
62-
# define PLLM 8
63-
# define PLLN 336
64-
# define PLLP 2
65-
# define PLLQ 7
62+
# if defined(STM32_PLLM) && defined(STM32_PLLN) && \
63+
defined(STM32_PLLP) && defined(STM32_PLLQ)
64+
# define PLLM STM32_PLLM
65+
# define PLLN STM32_PLLN
66+
# define PLLP STM32_PLLP
67+
# define PLLQ STM32_PLLQ
68+
# else
69+
# define PLLM 8
70+
# define PLLN 336
71+
# define PLLP 2
72+
# define PLLQ 7
73+
# endif
6674
# define PLLR 0
6775
# define TARGET_FLASH_WAITSTATES 5
6876
#endif

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