4848/* Placeholder functions - to be implemented */
4949void hal_init (void )
5050{
51+ wolfBoot_printf ("wolfBoot Version: %s (%s %s)\n" ,
52+ LIBWOLFBOOT_VERSION_STRING ,__DATE__ , __TIME__ );
5153
5254}
5355
@@ -150,7 +152,8 @@ int mmc_set_timeout(uint32_t timeout_us)
150152
151153 /* read capabilities to determine timeout clock frequency and unit (MHz or kHz) */
152154 reg = EMMC_SD_SRS16 ;
153- tcfclk_khz = (reg * EMMC_SD_SRS16_TCF_MASK );
155+ tcfclk_khz = (reg & EMMC_SD_SRS16_TCF_MASK ) >> EMMC_SD_SRS16_TCF_SHIFT ;
156+ /* Default timeout clock frequency should be 50MHz */
154157
155158 if (((reg & EMMC_SD_SRS16_TCU ) == 0 ) && (timeout_us < 1000 )) {
156159 /* invalid timeout_us value */
@@ -184,14 +187,14 @@ int mmc_set_timeout(uint32_t timeout_us)
184187 }
185188 dtcv = i ;
186189
187- /* set the data timeout counter value - CHECK: 0xc0207 */
190+ /* set the data timeout counter value */
188191 reg = EMMC_SD_SRS11 ;
189192 reg &= ~EMMC_SD_SRS11_DTCV_MASK ;
190193 reg |= (dtcv << EMMC_SD_SRS11_DTCV_SHIFT ) & EMMC_SD_SRS11_DTCV_MASK ;
191194 EMMC_SD_SRS11 = reg ;
192195
193196#ifdef DEBUG_MMC
194- wolfBoot_printf ("mmc_set_timeout: dtcv 0x%08X, srs11 0x%08X \n" , dtcv , reg );
197+ wolfBoot_printf ("mmc_set_timeout: timeout_val %d (%d) \n" , timeout_val , dtcv );
195198#endif
196199
197200 return 0 ;
@@ -268,9 +271,6 @@ uint32_t mmc_set_clock(uint32_t clock_khz)
268271 }
269272 base_clk_khz *= 1000 ; /* convert MHz to kHz */
270273
271- /* select clock frequency */
272- reg = EMMC_SD_SRS11 ;
273- reg &= ~(EMMC_SD_SRS11_SDCFSL_MASK | EMMC_SD_SRS11_SDCFSH_MASK );
274274 /* calculate divider */
275275 for (i = 1 ; i < 2046 ; i ++ ) {
276276 if (((base_clk_khz / i ) < clock_khz ) ||
@@ -279,8 +279,12 @@ uint32_t mmc_set_clock(uint32_t clock_khz)
279279 }
280280 }
281281 mclk = (i / 2 );
282- reg |= ((mclk << EMMC_SD_SRS11_SDCFSL_SHIFT ) & EMMC_SD_SRS11_SDCFSL_MASK ) /* lower 8 bits */
283- | ((mclk << EMMC_SD_SRS11_SDCFSH_SHIFT ) & EMMC_SD_SRS11_SDCFSH_SHIFT ); /* upper 2 bits */
282+
283+ /* select clock frequency */
284+ reg = EMMC_SD_SRS11 ;
285+ reg &= ~(EMMC_SD_SRS11_SDCFSL_MASK | EMMC_SD_SRS11_SDCFSH_MASK );
286+ reg |= (((mclk & 0x0FF ) << EMMC_SD_SRS11_SDCFSL_SHIFT ) & EMMC_SD_SRS11_SDCFSL_MASK ); /* lower 8 bits */
287+ reg |= (((mclk & 0x300 ) << EMMC_SD_SRS11_SDCFSH_SHIFT ) & EMMC_SD_SRS11_SDCFSH_SHIFT ); /* upper 2 bits */
284288 reg |= EMMC_SD_SRS11_ICE ; /* clock enable */
285289 reg &= ~EMMC_SD_SRS11_CGS ; /* select clock */
286290 EMMC_SD_SRS11 = reg ;
@@ -383,7 +387,7 @@ int mmc_send_cmd(uint32_t cmd_index, uint32_t cmd_arg, uint8_t resp_type)
383387 /* check for device busy */
384388 if (resp_type == EMMC_SD_RESP_R1 || resp_type == EMMC_SD_RESP_R1B ) {
385389 uint32_t resp = EMMC_SD_SRS04 ;
386- #define CARD_STATUS_READY_FOR_DATA (0x1 << 8)
390+ #define CARD_STATUS_READY_FOR_DATA (1U << 8)
387391 if ((resp & CARD_STATUS_READY_FOR_DATA ) == 0 ) {
388392 status = DEVICE_BUSY ; /* card is busy */
389393 }
@@ -469,13 +473,26 @@ int mmc_block_read(uint32_t cmd_index, uint32_t block_addr, uint32_t* dst,
469473 /* wait for command and data line busy to clear */
470474 while ((EMMC_SD_SRS09 & (EMMC_SD_SRS09_CICMD | EMMC_SD_SRS09_CIDAT )) != 0 );
471475
472- EMMC_SD_SRS01 = block_addr ; /* cmd argument */
476+ if (cmd_index == SD_ACMD51_SEND_SCR ) {
477+ status = mmc_send_cmd (SD_CMD_16 , sz , EMMC_SD_RESP_R1 );
478+ if (status == 0 ) {
479+ status = mmc_send_cmd (SD_CMD55_APP_CMD , (g_rca << SD_RCA_SHIFT ),
480+ EMMC_SD_RESP_R1 );
481+ }
482+ status = 0 ; /* ignore error */
483+ }
484+
485+ #ifdef DEBUG_MMC
486+ wolfBoot_printf ("mmc_block_read: cmd_index: %d, block_addr: %08X, dst %p, sz: %d\n" ,
487+ cmd_index , block_addr , dst , sz );
488+ #endif
489+
490+ EMMC_SD_SRS02 = block_addr ; /* cmd argument */
473491 /* execute command */
474492 EMMC_SD_SRS03 = ((cmd_index << EMMC_SD_SRS03_CIDX_SHIFT ) |
475493 EMMC_SD_SRS03_DPS | EMMC_SD_SRS03_DTDS |
476494 EMMC_SD_SRS03_BCE | EMMC_SD_SRS03_RECE | EMMC_SD_SRS03_RID |
477- EMMC_SD_SRS03_RECT | EMMC_SD_SRS03_RESP_48 | EMMC_SD_SRS03_CRCCE |
478- EMMC_SD_SRS03_CICE );
495+ EMMC_SD_SRS03_RESP_48 | EMMC_SD_SRS03_CRCCE | EMMC_SD_SRS03_CICE );
479496
480497 /* wait for buffer read ready */
481498 while (((reg = EMMC_SD_SRS12 ) & (EMMC_SD_SRS12_BRR | EMMC_SD_SRS12_EINT )) == 0 );
@@ -489,15 +506,17 @@ int mmc_block_read(uint32_t cmd_index, uint32_t block_addr, uint32_t* dst,
489506 }
490507 }
491508
492- /* check for any errors */
509+ /* check for any errors and wait for idle */
493510 reg = EMMC_SD_SRS12 ;
494- if (reg & EMMC_SD_SRS12_ERR_STAT ) {
511+ if ((reg & EMMC_SD_SRS12_ERR_STAT ) == 0 ) {
512+ mmc_delay (0xFF );
513+ status = mmc_wait_busy (0 );
514+ }
515+ else {
495516 #ifdef DEBUG_MMC
496517 wolfBoot_printf ("mmc_block_read: error: 0x%08X\n" , reg );
497518 #endif
498- /* wait for idle */
499- mmc_delay (0xFF );
500- status = mmc_wait_busy (0 );
519+ status = -1 ;
501520 }
502521
503522 return status ;
@@ -538,7 +557,7 @@ static uint32_t get_srs_bits(int from, int count)
538557 int off , shft ;
539558
540559 from -= 8 ;
541- mask = (count < 32 ? 1 << count : 0 ) - 1 ;
560+ mask = (( count < 32 ) ? ( 1U << ( uint32_t ) count ) : 0 ) - 1 ;
542561 off = from / 32 ;
543562 shft = from & 31 ;
544563 ret = resp [off ] >> shft ;
@@ -785,13 +804,13 @@ int mmc_init(void)
785804 #define SECT_SIZE_CSD_SHIFT 14
786805 c_size = (EMMC_SD_SRS04 & SECT_SIZE_CSD_MASK ) >> SECT_SIZE_CSD_SHIFT ;
787806 if (c_size < 32 ) {
788- g_sector_size = (1 << c_size );
807+ g_sector_size = (1U << c_size );
789808 #ifdef DEBUG_MMC
790809 wolfBoot_printf ("mmc_init: sector size: %d\n" , g_sector_size );
791810 #endif
792811 }
793812
794- csd_struct = get_srs_bits (126 ,2 );
813+ csd_struct = get_srs_bits (126 , 2 );
795814 switch (csd_struct ) {
796815 case 0 :
797816 c_size = get_srs_bits (62 , 12 );
@@ -829,16 +848,8 @@ int mmc_init(void)
829848 if (status == 0 ) {
830849 /* Get SCR registers - 8 bytes */
831850 uint32_t scr_reg [SCR_REG_DATA_SIZE /sizeof (uint32_t )];
832-
833- status = mmc_send_cmd (SD_CMD_16 , sizeof (scr_reg ), EMMC_SD_RESP_R1 );
834- if (status == 0 ) {
835- status = mmc_send_cmd (SD_CMD55_APP_CMD , (g_rca << SD_RCA_SHIFT ),
836- EMMC_SD_RESP_R1 );
837- }
838- if (status == 0 ) {
839- status = mmc_block_read (SD_ACMD51_SEND_SCR , 0 , scr_reg ,
840- sizeof (scr_reg ));
841- }
851+ status = mmc_block_read (SD_ACMD51_SEND_SCR , 0 , scr_reg ,
852+ sizeof (scr_reg ));
842853 }
843854 if (status == 0 ) {
844855 /* set UHS mode to SDR25 and driver strength to Type B */
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