Fixes to get H5 SPI working

Author: dgarske

hal/spi/spi_drv_stm32.c

@@ -83,6 +83,8 @@ void RAMFUNCTION stm_gpio_config(uint32_t base, uint32_t pin, uint32_t mode,
 
     /* Enable GPIO clock */
     RCC_GPIO_CLOCK_ER |= (1 << base_num);
+    /* Delay after an RCC peripheral clock enabling */
+    reg = RCC_GPIO_CLOCK_ER;
 
     /* Set Mode and Alternate Function */
     reg = GPIO_MODE(base) & ~(0x03UL << (pin * 2));
@@ -112,6 +114,10 @@ void RAMFUNCTION stm_gpio_config(uint32_t base, uint32_t pin, uint32_t mode,
     /* configure output speed 0=low, 1=med, 2=high, 3=very high */
     reg = GPIO_OSPD(base) & ~(0x03UL << (pin * 2));
     GPIO_OSPD(base) |= (speed << (pin * 2));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+#endif
 }
 
 #if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
@@ -373,7 +379,7 @@ uint8_t RAMFUNCTION spi_read(void)
 #ifdef SPI1_RXDR
     return SPI1_RXDR;
 #else
-    return SPI1_DR
+    return SPI1_DR;
 #endif
 }
 
@@ -490,10 +496,12 @@ void RAMFUNCTION spi_init(int polarity, int phase)
         /* Configure SPI1 for master mode */
         SPI1_CR1 &= ~SPI_CR1_SPI_EN;
     #if defined(TARGET_stm32h5)
-        /* baud rate 2 (hclk/8), data size 8 bits, FIFO threshold level (8-data) */
+        /* baud rate 2 (hclk/8), data size (8-bits), CRC Size (8-bits),
+         * FIFO threshold level (1-data) */
         SPI1_CFG1 = (
-            ((7 & SPI_CFG1_FTHLV_MASK) << SPI_CFG1_FTHLV_SHIFT) |
             ((2 & SPI_CFG1_BAUDRATE_MASK) << SPI_CFG1_BAUDRATE_SHIFT) |
+            ((7 & SPI_CFG1_CRCSIZE_MASK) << SPI_CFG1_CRCSIZE_SHIFT) |
+            ((0 & SPI_CFG1_FTHLV_MASK) << SPI_CFG1_FTHLV_SHIFT) |
             ((7 & SPI_CFG1_DSIZE_MASK) << SPI_CFG1_DSIZE_SHIFT));
         SPI1_CFG2 = SPI_CRF2_MASTER | SPI_CFG2_SSOE |
             (polarity << SPI_CFG2_CLOCK_POL_SHIFT) |

hal/spi/spi_drv_stm32.h

@@ -29,7 +29,6 @@
 #define GPIOC_BASE (0x40020800)
 #define GPIOD_BASE (0x40020C00)
 #define GPIOE_BASE (0x40021000)
-#define GPIO_BASE GPIOA_BASE
 #define SPI_GPIO      GPIOB_BASE
 #define SPI_CS_GPIO   GPIOE_BASE
 #define SPI_CS_FLASH  1 /* Flash CS connected to GPIOE1 */
@@ -44,9 +43,9 @@
 #ifdef TARGET_stm32h5
 #include "hal/stm32h5.h"
 
-#define RCC_GPIO_CLOCK_ER  RCC_AHB2ENR_CLOCK_ER
 #define APB2_CLOCK_RST     RCC_APB2_CLOCK_RSTR
 #define APB2_CLOCK_ER      RCC_APB2_CLOCK_ER
+#define RCC_GPIO_CLOCK_ER  RCC_AHB2ENR_CLOCK_ER
 
 /* Nucleo STM32H573ZI SPI_A Port (SPI1) */
 #define SPI_CLOCK_PIO_BASE  GPIOA_BASE
@@ -437,14 +436,15 @@
 #define SPI1_TXDR     (*(volatile uint8_t *)(SPI1_BASE + 0x20))
 #define SPI1_RXDR     (*(volatile uint8_t *)(SPI1_BASE + 0x30))
 
-#define SPI_CR1_SPI_EN              (1 << 6)
+#define SPI_CR1_SPI_EN              (1 << 0)
 #define SPI_CR1_CSTART              (1 << 9) /* Continous start */
+
 #define SPI_CFG1_DSIZE_MASK         (0x1F)
 #define SPI_CFG1_DSIZE_SHIFT        (0)
-
 #define SPI_CFG1_FTHLV_MASK         (0x1F)
 #define SPI_CFG1_FTHLV_SHIFT        (5)
-
+#define SPI_CFG1_CRCSIZE_MASK       (0x1F)
+#define SPI_CFG1_CRCSIZE_SHIFT      (16)
 #define SPI_CFG1_BAUDRATE_MASK      (0x07)
 #define SPI_CFG1_BAUDRATE_SHIFT     (28)
 
@@ -458,8 +458,8 @@
 #define SPI_CFG2_COMM_MASK          (0x3) /* 0=full duplex, 1=simplex tx, 2=simplex rx, 3=half duplex */
 #define SPI_CFG2_COMM_SHIFT         (17)
 
-#define SPI_SR_RX_NOTEMPTY          (1 << 0)
-#define SPI_SR_TX_EMPTY             (1 << 1)
+#define SPI_SR_RX_NOTEMPTY          (1UL << 0)
+#define SPI_SR_TX_EMPTY             (1UL << 1)
 
 #else
 
@@ -499,6 +499,9 @@
 #define GPIO_BSRR(base)    (*(volatile uint32_t *)(base + 0x18)) /* GPIOx_BSRR */
 #define GPIO_AFL(base)     (*(volatile uint32_t *)(base + 0x20)) /* GPIOx_AFRL */
 #define GPIO_AFH(base)     (*(volatile uint32_t *)(base + 0x24)) /* GPIOx_AFRH */
+#ifndef GPIO_SECCFGR
+#define GPIO_SECCFGR(base) (*(volatile uint32_t *)(base + 0x30)) /* GPIOx_SECCFGR */
+#endif
 
 #define GPIO_MODE_INPUT  (0)
 #define GPIO_MODE_OUTPUT (1)

hal/stm32h5.c

@@ -272,24 +272,25 @@ static void clock_pll_off(void)
 
 }
 
-/*This implementation will setup MSI 48 MHz as PLL Source Mux, PLLCLK as System Clock Source*/
+/* If PLL_SRC_HSE is set then HSE (8MHz) is used otherwise HSI 64 MHz is used
+ * and system clock is 250MHz */
 
 static void clock_pll_on(void)
 {
     uint32_t reg32;
     uint32_t plln, pllm, pllq, pllp, pllr, hpre, apb1pre, apb2pre, apb3pre, flash_waitstates;
 
 #if PLL_SRC_HSE
-    pllm = 4;
-    plln = 250;
-    pllp = 2;
-    pllq = 2;
+    pllm = 1;
+    plln = 62;
+    pllp = 2; /* 250Mhz */
+    pllq = 5; /* 100Mhz */
     pllr = 2;
 #else
-    pllm = 1;
-    plln = 129;
+    pllm = 4;
+    plln = 31;
     pllp = 2;
-    pllq = 2;
+    pllq = 5;
     pllr = 2;
 #endif
     flash_waitstates = 5;
@@ -432,8 +433,8 @@ static void periph_unsecure(void)
     volatile uint32_t *nvic_itns;
     uint32_t nvic_reg_pos, nvic_reg_off;
 
-    /*Enable clock for User LED GPIOs */
-    RCC_AHB2_CLOCK_ER|= LED_AHB2_ENABLE;
+    /* Enable clock for User LED GPIOs */
+    RCC_AHB2_CLOCK_ER |= LED_AHB2_ENABLE;
 
     /* Enable GPIO clock for accessing SECCFGR registers */
     RCC_AHB2_CLOCK_ER |= GPIOA_AHB2_CLOCK_ER;
@@ -449,10 +450,10 @@ static void periph_unsecure(void)
 
 
     PWR_CR2 |= PWR_CR2_IOSV;
-    /*Un-secure User LED GPIO pins */
-    GPIO_SECCFGR(GPIOG_BASE) &= ~(1 << 4);
-    GPIO_SECCFGR(GPIOB_BASE) &= ~(1 << 0);
-    GPIO_SECCFGR(GPIOF_BASE) &= ~(1 << 4);
+    /* Un-secure User LED GPIO pins */
+    GPIO_SECCFGR(GPIOG_BASE) &= ~(1 << LED_BOOT_PIN);  /* PG4 - Nucleo board - Orange Led */
+    GPIO_SECCFGR(GPIOB_BASE) &= ~(1 << LED_USR_PIN);   /* PB0 - Nucleo board - Green Led */
+    GPIO_SECCFGR(GPIOF_BASE) &= ~(1 << LED_EXTRA_PIN); /* PF4 - Nucleo board - Blue Led */
 
     /* Unsecure LPUART1 */
     GPIO_SECCFGR(GPIOB_BASE) &= ~(1<<UART1_TX_PIN);
@@ -478,17 +479,6 @@ static void periph_unsecure(void)
     nvic_reg_off = NVIC_USART3_IRQ % 32;
     nvic_itns = ((volatile uint32_t *)(NVIC_ITNS_BASE + 4 * nvic_reg_pos));
     *nvic_itns |= (1 << nvic_reg_off);
-
-
-    /* Disable GPIOs clock used previously for accessing SECCFGR registers */
-#if 0
-    RCC_AHB2_CLOCK_ER &= ~GPIOA_AHB2_CLOCK_ER;
-    RCC_AHB2_CLOCK_ER &= ~GPIOB_AHB2_CLOCK_ER;
-    RCC_AHB2_CLOCK_ER &= ~GPIOC_AHB2_CLOCK_ER;
-    RCC_AHB2_CLOCK_ER &= ~GPIOD_AHB2_CLOCK_ER;
-#endif
-
-
 }
 #endif
 

test-app/app_stm32h5.c

@@ -150,9 +150,6 @@ void extra_led_off(void)
     GPIOF_BSRR |= (1 << (LED_EXTRA_PIN + 16));
 }
 
-static char CaBuf[2048];
-static uint8_t my_pubkey[200];
-
 extern int ecdsa_sign_verify(int devId);
 
 /* Command line commands */
@@ -545,9 +542,10 @@ static int cmd_timestamp(const char *args)
 {
     struct timespec tp = {};
     clock_gettime(0, &tp);
-    printf("Current timestamp: %llu.%03lu\r\n", tp.tv_sec, tp.tv_nsec/1000000);
+    printf("Current timestamp: %lu.%03lu\r\n",
+        (long unsigned int)tp.tv_sec, tp.tv_nsec/1000000);
     printf("Current systick: %u\r\n", jiffies);
-    printf("VTOR: %08lx\r\n", (*(volatile uint32_t *)(0xE000ED08)));
+    printf("VTOR: 0x%08lx\r\n", (*(volatile uint32_t *)(0xE000ED08)));
     return 0;
 }