Support for Microchip PolarFire SoC (MPFS250)

Author: trini

.github/workflows/test-configs.yml

@@ -184,6 +184,13 @@ jobs:
       arch: arm
       config-file: ./config/examples/mcxw.config
 
+  # TODO: polarfire_mpfs250.config requires PolarFire SoC SDK
+  #polarfire_mpfs250_test:
+  #  uses: ./.github/workflows/test-build-mcux-sdk.yml
+  #  with:
+  #    arch: riscv64
+  #    config-file: ./config/examples/polarfire_mpfs250.config
+
   raspi3_test:
     uses: ./.github/workflows/test-build.yml
     with:

arch.mk

@@ -557,6 +557,37 @@ ifeq ($(ARCH),RISCV)
   ARCH_FLASH_OFFSET=0x20010000
 endif
 
+## RISCV64
+ifeq ($(ARCH),RISCV64)
+  CROSS_COMPILE?=riscv64-unknown-elf-
+  CFLAGS+=-DMMU -DWOLFBOOT_DUALBOOT
+  UPDATE_OBJS:=src/update_ram.o
+  ARCH_FLAGS=-march=rv64imafdc -mabi=lp64d -mcmodel=medany
+  CFLAGS+=-fno-builtin-printf -DUSE_M_TIME -g -nostartfiles -DARCH_RISCV64
+  CFLAGS+=$(ARCH_FLAGS)
+  LDFLAGS+=$(ARCH_FLAGS)
+
+  # Prune unused functions and data
+  CFLAGS +=-ffunction-sections -fdata-sections
+  LDFLAGS+=-Wl,--gc-sections
+
+  OBJS+=src/boot_riscv64_start.o src/boot_riscv64.o src/vector_riscv64.o
+  ARCH_FLASH_OFFSET=0x20220000
+
+  OBJS+=src/fdt.o
+
+  ifeq ($(SPMATH),1)
+    MATH_OBJS += $(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/sp_c64.o
+  endif
+
+  ifneq ($(NO_ASM),1)
+    MATH_OBJS+=$(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/port/riscv/riscv-64-sha256.o \
+               $(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/port/riscv/riscv-64-sha512.o \
+               $(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/port/riscv/riscv-64-sha3.o \
+               $(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/port/riscv/riscv-64-aes.o
+  endif
+endif
+
 # powerpc
 ifeq ($(ARCH),PPC)
   CROSS_COMPILE?=powerpc-linux-gnu-

config/examples/polarfire_mpfs250.config

@@ -0,0 +1,54 @@
+ARCH?=RISCV64
+TARGET?=mpfs250
+SIGN?=ECC384
+HASH?=SHA384
+IMAGE_HEADER_SIZE=512
+WOLFBOOT_VERSION?=1
+ARMORED?=0
+DEBUG?=0
+DEBUG_SYMBOLS?=1
+DEBUG_UART?=1
+VTOR?=1
+EXT_FLASH?=1
+SPI_FLASH?=0
+NO_XIP?=1
+NVM_FLASH_WRITEONCE?=0
+UART_FLASH?=0
+V?=0
+NO_MPU?=1
+RAM_CODE?=0
+SPMATH?=1
+DUALBANK_SWAP?=0
+PKA?=0
+ENCRYPT=0
+WOLFTPM?=0
+
+# Optionally allow downgrade to older valid version in update partition
+ALLOW_DOWNGRADE?=0
+
+# Use assembly version of ECDSA and SHA
+NO_ASM?=0
+NO_ARM_ASM?=0
+
+# Optional: Use smaller SHA512
+#CFLAGS_EXTRA+=-DUSE_SLOW_SHA512
+
+# Flash sector size (4KB typical)
+WOLFBOOT_SECTOR_SIZE?=0x1000
+
+# Load Partition to RAM Address
+WOLFBOOT_LOAD_ADDRESS?=0xA0000000
+
+# Partition layout for PolarFire SoC MPFS250T
+# TODO: Update with actual flash layout based on your system design
+WOLFBOOT_PARTITION_SIZE?=0x10000
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08080000
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x08090000
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x080FF000
+
+# DTS (Device Tree)
+WOLFBOOT_LOAD_DTS_ADDRESS?=0x80000000
+WOLFBOOT_DTS_BOOT_ADDRESS?=0x20F00000
+WOLFBOOT_DTS_UPDATE_ADDRESS?=0x20F00000
+
+#CFLAGS_EXTRA+=-DDEBUG_EXT_FLASH

docs/Targets.md

@@ -12,6 +12,7 @@ This README describes configuration of supported targets.
 * [Kontron VX3060-S2](#kontron-vx3060-s2)
 * [Microchip PIC32CK](#microchip-pic32ck)
 * [Microchip PIC32CZ](#microchip-pic32cz)
+* [Microchip PolarFire SoC](#microchip-polarfire-soc)
 * [Microchip SAMA5D3](#microchip-sama5d3)
 * [Microchip SAME51](#microchip-same51)
 * [Nordic nRF52840](#nordic-nrf52840)
@@ -778,6 +779,110 @@ add-symbol-file test-app/image.elf 0x20020100
 ```
 
 
+## Microchip PolarFire SoC
+
+The PolarFire SoC is a 64-bit RISC-V SoC featuring a five-core CPU cluster (1× E51 monitor core and 4× U54 application cores) and FPGA fabric. Tested with MPFS250.
+
+### Features
+* RISC-V 64-bit architecture (rv64imac)
+* Five-core CPU: 1× E51 monitor + 4× U54 application cores
+* Integrated DDR3/4, LPDDR3/4 controller and PHY
+* PCIe Gen2, USB 2.0, and Gigabit Ethernet interfaces
+* Secure boot capabilities
+* Low power consumption
+* External flash support
+
+### Building PolarFire SoC
+
+All build settings come from .config file. For this platform use `TARGET=mpfs250` and `ARCH=RISCV64`.
+
+See example configuration at `config/examples/polarfire_mpfs250.config`.
+
+```sh
+cp config/examples/polarfire_mpfs250.config .config
+make wolfboot.elf
+```
+
+To assemble this as a flashable image you need the 0x100 byte HART header added:
+
+```sh
+git clone https://github.com/polarfire-soc/hart-software-services.git
+cd hart-software-services
+cd tools/hss-payload-generator
+make
+# install tool
+sudo cp hss-payload-generator /usr/local/bin/
+```
+
+Use this command to assemble a bootable wolfboot image:
+
+```sh
+hss-payload-generator -vvv -c ./hal/mpfs.yaml wolfboot.bin
+```
+
+Any customizations to the Device Tree can be made in mpfs.dts and it can be recompiled using: `dtc -I dts -O dtb mpfs.dts -o mpfs.dtb`
+
+
+Example one-shot command:
+
+```sh
+cp ./config/examples/polarfire_mpfs250.config .config && make clean && make wolfboot.elf && size wolfboot.elf && hss-payload-generator -vvv -c ./hal/mpfs.yaml wolfboot.bin && file wolfboot.bin && ls -la wolfboot.bin
+```
+
+### Flashing PolarFire SoC
+
+
+The HSS MMC boot source looks for GPT with GUID "21686148-6449-6E6F-744E-656564454649" or sector "0" if no GPT found. That GUID is the default "BIOS" boot partition.
+
+The resulting image from `hss-payload-generator` can be directly placed into GPT BIOS partition. The HSS tinyCLI supports the `USBDMSC` command to mount the eMMC or SD card as a USB device. You can then use "dd" to copy the boot image to the BOOT partition 2. Example:
+
+```
+sudo dd if=wolfboot.bin of=/dev/sde2 bs=1024
+```
+
+Flashing to eNVM:
+
+The boot rom expects a 0x100 byte secure boot header added. It also requires the .ld is offset by 0x100 to leave room for this. The mpfsBootmodeProgrammer adds 0x100 of meta information for secure boot.
+
+```sh
+$SC_INSTALL_DIR/eclipse/jre/bin/java -jar \
+    $SC_INSTALL_DIR/extras/mpfs/mpfsBootmodeProgrammer.jar \
+    --bootmode 1 --die MPFS250T --package FCVG484 --workdir $PWD wolfboot.elf
+```
+Note: wolfBoot does not support running from eNVM in machine mode yet.
+
+### Debugging PolarFire Soc
+
+Start GDB server:
+
+```sh
+$SC_INSTALL_DIR/openocd/bin/openocd --command "set DEVICE MPFS" --file board/microsemi-riscv.cfg
+```
+
+Start GDB Client: `riscv64-unknown-elf-gdb`
+
+```
+file wolfboot.elf
+tar rem:3333
+add-symbol-file ../hart-software-services/build/hss-l2scratch.elf
+set pagination off
+foc c
+
+set $target_riscv=1
+set mem inaccessible-by-default off
+set architecture riscv:rv64
+#load wolfboot.elf
+#thread apply 2 set $pc=_reset
+#thread apply all set $pc=_start
+```
+
+### PolarFire TODO
+
+1) Add support for full HSS replacement using wolfboot.
+2) Add support for eMMC and QSPI NOR flash
+
+
+
 ## STM32F7
 
 The STM32-F76x and F77x offer dual-bank hardware-assisted swapping.