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Export hal functions for OTP read/write access
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-301
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5 files changed

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‎hal/stm32h7.c‎

Lines changed: 7 additions & 300 deletions
Original file line numberDiff line numberDiff line change
@@ -19,302 +19,7 @@
1919
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
2020
*/
2121

22-
#include <stdint.h>
23-
#include "image.h"
24-
#include "hal.h"
25-
26-
/* Assembly helpers */
27-
#define DMB() __asm__ volatile ("dmb")
28-
#define ISB() __asm__ volatile ("isb")
29-
#define DSB() __asm__ volatile ("dsb")
30-
31-
/* STM32 H7 register configuration */
32-
/*** RCC ***/
33-
#define RCC_BASE (0x58024400) /* RM0433 - Table 8 */
34-
#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00)) /* RM0433 - 7.7.2 */
35-
#define RCC_PLLCKSELR (*(volatile uint32_t *)(RCC_BASE + 0x28)) /* RM0433 - 7.7.11 */
36-
#define RCC_PLLCFGR (*(volatile uint32_t *)(RCC_BASE + 0x2C)) /* RM0433 - 7.7.12 */
37-
#define RCC_PLL1DIVR (*(volatile uint32_t *)(RCC_BASE + 0x30)) /* RM0433 - 7.7.13 */
38-
39-
#define RCC_CFGR (*(volatile uint32_t *)(RCC_BASE + 0x10)) /* RM0433 - 7.7.7 */
40-
#define RCC_D1CFGR (*(volatile uint32_t *)(RCC_BASE + 0x18)) /* RM0433 - 7.7.8 */
41-
#define RCC_D2CFGR (*(volatile uint32_t *)(RCC_BASE + 0x1C)) /* RM0433 - 7.7.8 */
42-
#define RCC_D3CFGR (*(volatile uint32_t *)(RCC_BASE + 0x20)) /* RM0433 - 7.7.9 */
43-
44-
#define RCC_D2CCIP2R (*(volatile uint32_t *)(RCC_BASE + 0x54)) /* RM0433 - 8.7.21 */
45-
46-
#define APB1_CLOCK_LRST (*(volatile uint32_t *)(RCC_BASE + 0x90)) /* RM0433 - 8.7.33 - RCC_APB1LRSTR */
47-
48-
#define AHB4_CLOCK_ENR (*(volatile uint32_t *)(RCC_BASE + 0xE0)) /* RM0433 - 8.7.43 */
49-
#define APB1_CLOCK_LER (*(volatile uint32_t *)(RCC_BASE + 0xE8)) /* RM0433 - 8.7.45 - RCC_APB1LENR */
50-
#define APB1_CLOCK_HER (*(volatile uint32_t *)(RCC_BASE + 0xEC)) /* RM0433 - 8.7.46 */
51-
#define APB2_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0xF0)) /* RM0433 - 8.7.47 */
52-
#define AHB3_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0xD4)) /* RM0433 - 8.7.40 */
53-
54-
#define RCC_CR_PLL1RDY (1 << 25)
55-
#define RCC_CR_PLL1ON (1 << 24)
56-
#define RCC_CR_HSEBYP (1 << 18)
57-
#define RCC_CR_HSERDY (1 << 17)
58-
#define RCC_CR_HSEON (1 << 16)
59-
#define RCC_CR_HSIRDY (1 << 2)
60-
#define RCC_CR_HSION (1 << 0)
61-
62-
#define RCC_CFGR_SW_HSISYS 0x0
63-
#define RCC_CFGR_SW_PLL 0x3
64-
#define RCC_PLLCFGR_DIVR1EN (1 << 18)
65-
#define RCC_PLLCFGR_DIVQ1EN (1 << 17)
66-
#define RCC_PLLCFGR_DIVP1EN (1 << 16)
67-
68-
#define RCC_PLLCFGR_PLL1VCOSEL (1 << 1)
69-
70-
#define RCC_PLLCFGR_PLL1RGE_2_4 0x1
71-
#define RCC_PLLCFGR_PLL1RGE_SHIFT 0x2
72-
73-
#define RCC_PLLCKSELR_DIVM1 (1 << 4)
74-
#define RCC_PLLCKSELR_PLLSRC_HSI 0x0
75-
#define RCC_PLLCKSELR_PLLSRC_HSE 0x2
76-
77-
#define RCC_PLLCKSELR_DIVM1_NONE 0x1
78-
79-
/*** GPIO ***/
80-
#define GPIOA_BASE (0x58020000)
81-
#define GPIOB_BASE (0x58020400)
82-
#define GPIOC_BASE (0x58020800)
83-
#define GPIOD_BASE (0x58020C00)
84-
#define GPIOE_BASE (0x58021000)
85-
#define GPIOF_BASE (0x58021400)
86-
#define GPIOG_BASE (0x58021800)
87-
88-
#define GPIO_MODE(base) (*(volatile uint32_t *)((base) + 0x00))
89-
#define GPIO_OTYPE(base) (*(volatile uint32_t *)((base) + 0x04))
90-
#define GPIO_OSPD(base) (*(volatile uint32_t *)((base) + 0x08))
91-
#define GPIO_PUPD(base) (*(volatile uint32_t *)((base) + 0x0c))
92-
#define GPIO_ODR(base) (*(volatile uint32_t *)((base) + 0x14))
93-
#define GPIO_BSRR(base) (*(volatile uint32_t *)((base) + 0x18))
94-
#define GPIO_AFRL(base) (*(volatile uint32_t *)((base) + 0x20))
95-
#define GPIO_AFRH(base) (*(volatile uint32_t *)((base) + 0x24))
96-
97-
98-
/*** PWR ***/
99-
#define PWR_BASE (0x58024800) /* RM0433 - Table 8 */
100-
#define PWR_CSR1 (*(volatile uint32_t *)(PWR_BASE + 0x04)) /* RM0433 - 5.8.x */
101-
#define PWR_CSR1_ACTVOSRDY (1 << 13)
102-
#define PWR_CR3 (*(volatile uint32_t *)(PWR_BASE + 0x0C)) /* RM0433 - 5.8.4 */
103-
#define PWR_CR3_SCUEN (1 << 2)
104-
#define PWR_CR3_LDOEN (1 << 1)
105-
#define PWR_D3CR (*(volatile uint32_t *)(PWR_BASE + 0x18)) /* RM0433 - 5.8.6 */
106-
#define PWR_D3CR_VOSRDY (1 << 13)
107-
#define PWR_D3CR_VOS_SHIFT (14)
108-
#define PWR_D3CR_VOS_SCALE_1 (3)
109-
110-
#define SYSCFG_BASE (0x58000400) /* RM0433 - Table 8 */
111-
#define SYSCFG_PMCR (*(volatile uint32_t *)(SYSCFG_BASE + 0x04)) /* RM0433 - 5.8.4 */
112-
#define SYSCFG_PWRCR (*(volatile uint32_t *)(SYSCFG_BASE + 0x04)) /* RM0433 - 5.8.4 */
113-
#define SYSCFG_UR0 (*(volatile uint32_t *)(SYSCFG_BASE + 0x300)) /* RM0433 - 12.3.1.2 */
114-
#define SYSCFG_PWRCR_ODEN (1 << 0)
115-
#define SYSCFG_UR0_BKS (1 << 0) /* bank swap */
116-
117-
/*** APB PRESCALER ***/
118-
#define RCC_PRESCALER_DIV_NONE 0
119-
#define RCC_PRESCALER_DIV_2 8
120-
121-
122-
/*** UART ***/
123-
#ifndef CLOCK_SPEED
124-
#define CLOCK_SPEED 64000000UL /* 120MHz pclk1, 64MHz HSI */
125-
#endif
126-
#ifndef BAUD_RATE
127-
#define BAUD_RATE 115200
128-
#endif
129-
#ifndef UART_PORT
130-
#define UART_PORT 3 /* default to Nucleo VCOM port */
131-
#endif
132-
133-
#if UART_PORT == 3
134-
/* USART3 Base address (connected to ST virtual com port on Nucleo board) */
135-
#define UART_BASE (0x40004800)
136-
#define UART_GPIO_BASE GPIOD_BASE
137-
#define UART_TX_PIN 8 /* PD8, USART Transmit pin */
138-
#define UART_RX_PIN 9 /* PD9, USART Receive pin */
139-
#define UART_PIN_AF 7 /* AF stands for Alternate Function. USART TX/RX */
140-
#elif UART_PORT == 5
141-
/* USART5 Base address */
142-
#define UART_BASE (0x40005000)
143-
#define UART_GPIO_BASE GPIOB_BASE
144-
#define UART_TX_PIN 13 /* PB13, USART Transmit pin */
145-
#define UART_RX_PIN 12 /* PB12, USART Receive pin */
146-
#define UART_PIN_AF 14 /* AF stands for Alternate Function. USART TX/RX */
147-
#else
148-
/* USART2 Base address (chosen because of its pin layout on Nucleo board) */
149-
#define UART_BASE (0x40004400)
150-
#define UART_GPIO_BASE GPIOD_BASE
151-
#define UART_TX_PIN 5 /* PD5, USART Transmit pin */
152-
#define UART_RX_PIN 6 /* PD6, USART Receive pin */
153-
#define UART_PIN_AF 7 /* AF stands for Alternate Function. USART TX/RX */
154-
#endif
155-
156-
/* UART/USART: Defining register start addresses. */
157-
#define UART_CR1(base) (*(volatile uint32_t *)((base) + 0x00))
158-
#define UART_CR2(base) (*(volatile uint32_t *)((base) + 0x04))
159-
#define UART_CR3(base) (*(volatile uint32_t *)((base) + 0x08))
160-
#define UART_BRR(base) (*(volatile uint32_t *)((base) + 0x0C))
161-
#define UART_RQR(base) (*(volatile uint32_t *)((base) + 0x18))
162-
#define UART_ISR(base) (*(volatile uint32_t *)((base) + 0x1C))
163-
#define UART_ICR(base) (*(volatile uint32_t *)((base) + 0x20))
164-
#define UART_RDR(base) (*(volatile uint32_t *)((base) + 0x24))
165-
#define UART_TDR(base) (*(volatile uint32_t *)((base) + 0x28))
166-
#define UART_PRESC(base) (*(volatile uint32_t *)((base) + 0x2C))
167-
168-
/* UART/USART: Defining register bit placement for CR1 and ISR register for readability. */
169-
#define UART_CR1_UART_ENABLE (1 << 0)
170-
#define UART_CR1_TX_ENABLE (1 << 3)
171-
#define UART_CR1_RX_ENABLE (1 << 2)
172-
#define UART_CR1_M1 (1 << 28)
173-
#define UART_CR1_M0 (1 << 12)
174-
#define UART_CR1_PARITY_ENABLED (1 << 10)
175-
#define UART_CR1_PARITY_ODD (1 << 9)
176-
#define UART_CR1_FIFOEN (1 << 29)
177-
#define UART_CR1_OVER8 (1 << 15)
178-
179-
#define UART_CR2_STOP_MASK (0x3 << 12)
180-
#define UART_CR2_STOP(bits) (((bits) & 0x3) << 12)
181-
#define UART_CR2_LINEN (1 << 14)
182-
#define UART_CR2_CLKEN (1 << 11)
183-
184-
#define UART_CR3_SCEN (1 << 5)
185-
#define UART_CR3_HDSEL (1 << 3)
186-
#define UART_CR3_IREN (1 << 1)
187-
188-
#define UART_ISR_TX_FIFO_NOT_FULL (1 << 7) /* Transmit Data Empty (TXE) or TX FIFO Not Full (TXFNF) */
189-
#define UART_ISR_RX_FIFO_NOT_EMPTY (1 << 5)
190-
#define UART_ISR_TRANSMISSION_COMPLETE (1 << 6)
191-
192-
/* RCC: Defining register bit placement for APB1, APB2, AHB1 and AHB4 register for readability. */
193-
#define RCC_APB1_USART2_EN (1 << 17)
194-
#define RCC_APB1_USART3_EN (1 << 18)
195-
#define RCC_APB1_UART4_EN (1 << 19)
196-
#define RCC_APB1_UART5_EN (1 << 20)
197-
#define RCC_APB1_UART7_EN (1 << 30)
198-
#define RCC_APB1_UART8_EN (1 << 31)
199-
#define RCC_APB2_USART1_EN (1 << 4)
200-
#define RCC_APB2_USART6_EN (1 << 5)
201-
202-
#define RCC_AHB4_GPIOB_EN (1 << 1)
203-
#define RCC_AHB4_GPIOD_EN (1 << 3)
204-
205-
/*** QSPI ***/
206-
/* See hal/spi/spi_drv_stm32.c */
207-
208-
209-
/*** FLASH ***/
210-
#define SYSCFG_APB4_CLOCK_ER_VAL (1 << 0) /* RM0433 - 7.7.48 - RCC_APB4ENR - SYSCFGEN */
211-
212-
#define FLASH_BASE (0x52002000) /* RM0433 - Table 8 */
213-
#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00)) /* RM0433 - 3.9.1 - FLASH_ACR */
214-
215-
#define FLASH_OPTKEYR (*(volatile uint32_t *)(FLASH_BASE + 0x08)) /* FLASH option key register */
216-
#define FLASH_OPTCR (*(volatile uint32_t *)(FLASH_BASE + 0x18)) /* FLASH option control register */
217-
#define FLASH_OPTSR_CUR (*(volatile uint32_t *)(FLASH_BASE + 0x1C)) /* FLASH option status register */
218-
219-
/* Bank 1 */
220-
#define FLASH_KEYR1 (*(volatile uint32_t *)(FLASH_BASE + 0x04)) /* RM0433 - 3.9.2 - FLASH_KEYR 1 */
221-
#define FLASH_CR1 (*(volatile uint32_t *)(FLASH_BASE + 0x0C)) /* RM0433 - 3.9.4 - FLASH_CR 1 */
222-
#define FLASH_SR1 (*(volatile uint32_t *)(FLASH_BASE + 0x10)) /* RM0433 - 3.9.5 - FLASH_SR 1 */
223-
224-
/* Bank 2 */
225-
#define FLASH_KEYR2 (*(volatile uint32_t *)(FLASH_BASE + 0x104)) /* RM0433 - 3.9.24 - FLASH_KEYR 2 */
226-
#define FLASH_SR2 (*(volatile uint32_t *)(FLASH_BASE + 0x110)) /* RM0433 - 3.9.26 - FLASH_SR 2 */
227-
#define FLASH_CR2 (*(volatile uint32_t *)(FLASH_BASE + 0x10C)) /* RM0433 - 3.9.25 - FLASH_CR 2 */
228-
229-
/* Flash Configuration */
230-
#define FLASHMEM_ADDRESS_SPACE (0x08000000UL)
231-
#define FLASH_PAGE_SIZE (0x20000) /* 128KB */
232-
#define FLASH_BANK2_BASE (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI */
233-
#define FLASH_BANK2_BASE_REL (FLASH_BANK2_BASE - FLASHMEM_ADDRESS_SPACE)
234-
#define FLASH_TOP (0x081FFFFFUL) /*!< FLASH end address */
235-
236-
/* Register values */
237-
#define FLASH_ACR_LATENCY_MASK (0x07)
238-
#define FLASH_SR_BSY (1 << 0)
239-
#define FLASH_SR_WBNE (1 << 1)
240-
#define FLASH_SR_QW (1 << 2)
241-
#define FLASH_SR_WRPERR (1 << 17)
242-
#define FLASH_SR_PGSERR (1 << 18)
243-
#define FLASH_SR_STRBERR (1 << 19)
244-
#define FLASH_SR_INCERR (1 << 21)
245-
#define FLASH_SR_OPERR (1 << 22)
246-
#define FLASH_SR_RDPERR (1 << 23)
247-
#define FLASH_SR_RDSERR (1 << 24)
248-
#define FLASH_SR_SNECCERR (1 << 25)
249-
#define FLASH_SR_DBECCERR (1 << 26)
250-
#define FLASH_SR_EOP (1 << 16)
251-
252-
#define FLASH_CR_LOCK (1 << 0) /* RM0433 - 3.7.5 - FLASH_CR */
253-
#define FLASH_CR_STRT (1 << 7)
254-
#define FLASH_CR_PSIZE (1 << 4)
255-
#define FLASH_CR_BER (1 << 3)
256-
#define FLASH_CR_SER (1 << 2)
257-
#define FLASH_CR_PG (1 << 1)
258-
#define FLASH_CR2_SPSS2 (1 << 14)
259-
260-
#define FLASH_OPTSR_CUR_BSY (1 << 0)
261-
262-
#define FLASH_OPTCR_OPTLOCK (1 << 0) /* lock option configuration bit */
263-
#define FLASH_OPTCR_OPTSTART (1 << 1) /* Option byte start change option configuration bit */
264-
#define FLASH_OPTCR_MER (1 << 4) /* Mass erase request */
265-
#define FLASH_OPTCR_PG_OTP (1 << 5) /* OTP program control bit */
266-
#define FLASH_OPTCR_OPTCHANGEERRIE (1 << 30) /* Option byte change error interrupt enable bit */
267-
#define FLASH_OPTCR_SWAP_BANK (1 << 31) /* Bank swapping option configuration bit */
268-
269-
#define FLASH_CR_SNB_SHIFT 8 /* SNB bits 10:8 */
270-
#define FLASH_CR_SNB_MASK 0x7 /* SNB bits 10:8 - 3 bits */
271-
272-
#define FLASH_KEY1 (0x45670123U)
273-
#define FLASH_KEY2 (0xCDEF89ABU)
274-
275-
#define FLASH_OPT_KEY1 (0x08192A3BU)
276-
#define FLASH_OPT_KEY2 (0x4C5D6E7FU)
277-
278-
#ifdef FLASH_OTP_ROT
279-
#ifndef FLASH_OTP_BASE
280-
#define FLASH_OTP_BASE 0x08FFF000
281-
#endif
282-
#ifndef FLASH_OTP_END
283-
#define FLASH_OTP_END 0x08FFF3FF
284-
#endif
285-
#ifndef OTP_SIZE
286-
#define OTP_SIZE 1024
287-
#endif
288-
#ifndef OTP_BLOCKS
289-
#define OTP_BLOCKS 16
290-
#endif
291-
292-
#define OTP_BLOCK_SIZE (OTP_SIZE / OTP_BLOCKS) /* 64 bytes */
293-
#endif
294-
295-
/* STM32H7: Due to ECC functionality, it is not possible to write partition/sector
296-
* flags and signature more than once. This flags_cache is used to intercept write operations and
297-
* ensures that the sector is always erased before each write.
298-
*/
299-
300-
#define STM32H7_SECTOR_SIZE 0x20000
301-
302-
#if defined(WOLFBOOT_PARTITION_SIZE) && \
303-
(WOLFBOOT_PARTITION_SIZE < (2 * STM32H7_SECTOR_SIZE))
304-
# error "Please use a bigger WOLFBOOT_PARTITION_SIZE, since the last 128KB on each partition will be reserved for bootloader flags"
305-
#endif
306-
307-
#define STM32H7_PART_BOOT_END (WOLFBOOT_PARTITION_BOOT_ADDRESS + WOLFBOOT_PARTITION_SIZE)
308-
#define STM32H7_PART_UPDATE_END (WOLFBOOT_PARTITION_UPDATE_ADDRESS + WOLFBOOT_PARTITION_SIZE)
309-
#define STM32H7_WORD_SIZE (32)
310-
#define STM32H7_PART_BOOT_FLAGS_PAGE_ADDRESS \
311-
(((STM32H7_PART_BOOT_END - 1) / STM32H7_SECTOR_SIZE) * STM32H7_SECTOR_SIZE)
312-
#define STM32H7_PART_UPDATE_FLAGS_PAGE_ADDRESS \
313-
(((STM32H7_PART_UPDATE_END - 1) / STM32H7_SECTOR_SIZE) * STM32H7_SECTOR_SIZE)
314-
#define STM32H7_BOOT_FLAGS_PAGE(x) \
315-
((x >= STM32H7_PART_BOOT_FLAGS_PAGE_ADDRESS) && (x < STM32H7_PART_BOOT_END))
316-
#define STM32H7_UPDATE_FLAGS_PAGE(x) \
317-
((x >= STM32H7_PART_UPDATE_FLAGS_PAGE_ADDRESS) && (x < STM32H7_PART_UPDATE_END))
22+
#include "hal/stm32h7.h"
31823

31924
static uint32_t stm32h7_cache[STM32H7_WORD_SIZE / sizeof(uint32_t)];
32025

@@ -809,8 +514,7 @@ void hal_prepare_boot(void)
809514
}
810515

811516
#ifdef FLASH_OTP_ROT
812-
813-
static void hal_flash_wait_otp(void)
517+
static void flash_otp_wait(void)
814518
{
815519
/* Wait for the FLASH operation to complete by polling on QW flag to be reset. */
816520
while ( (FLASH_SR1 & FLASH_SR_QW) == FLASH_SR_QW ) {
@@ -837,6 +541,8 @@ static void hal_flash_otp_lock(void)
837541
FLASH_OPTCR |= FLASH_OPTCR_OPTLOCK;
838542
}
839543

544+
/* Public API */
545+
840546
int hal_flash_otp_write(uint32_t flashAddress, uint16_t* data, uint16_t length)
841547
{
842548
volatile uint16_t tmp;
@@ -852,7 +558,7 @@ int hal_flash_otp_write(uint32_t flashAddress, uint16_t* data, uint16_t length)
852558
/* Clear errors */
853559
flash_clear_errors(0); /* bank 1 */
854560
/* Wait for last operation to be completed */
855-
hal_flash_wait_otp();
561+
flash_otp_wait();
856562

857563
FLASH_OPTCR &= ~(FLASH_OPTCR_OPTLOCK); /* unlock FLASH_OPTCR register */
858564

@@ -873,7 +579,7 @@ int hal_flash_otp_write(uint32_t flashAddress, uint16_t* data, uint16_t length)
873579
idx += sizeof(uint16_t);
874580

875581
/* Wait for last operation to be completed */
876-
hal_flash_wait_otp();
582+
flash_otp_wait();
877583

878584
/* clear OTP_PG bit */
879585
FLASH_OPTCR &= ~FLASH_OPTCR_PG_OTP;
@@ -902,3 +608,4 @@ int hal_flash_otp_read(uint32_t flashAddress, uint16_t* data, uint32_t length)
902608
}
903609

904610
#endif /* FLASH_OTP_ROT */
611+

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