Fixes for unused variables

dgarske · dgarske · commit 7c7f9d047be9 · 2025-11-18T14:27:35.000-08:00
diff --git a/Makefile b/Makefile
@@ -105,7 +105,7 @@ CFLAGS+= \
 # Setup default optimizations (for GCC)
 ifeq ($(USE_GCC_HEADLESS),1)
   CFLAGS+=-Wall -Wextra -Wno-main -ffreestanding -Wno-unused -nostartfiles
-  CFLAGS+=-ffunction-sections -fdata-sections -fomit-frame-pointer
+  CFLAGS+=-ffunction-sections -fdata-sections -fomit-frame-pointer -Wunused-variable
   LDFLAGS+=-Wl,-gc-sections -Wl,-Map=wolfboot.map -ffreestanding -nostartfiles
   # Not setting LDFLAGS directly since it is passed to the test-app
   LSCRIPT_FLAGS+=-T $(LSCRIPT)
diff --git a/arch.mk b/arch.mk
@@ -190,13 +190,14 @@ ifeq ($(ARCH),ARM)
     ARCH_FLASH_OFFSET=0x08000000
     SPI_TARGET=stm32
     ifneq ($(PKA),0)
-      PKA_EXTRA_OBJS+= $(STM32CUBE)/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pka.o  $(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/port/st/stm32.o
-      PKA_EXTRA_CFLAGS+=-DWOLFSSL_STM32_PKA -I$(STM32CUBE)/Drivers/STM32WBxx_HAL_Driver/Inc \
-          -Isrc -I$(STM32CUBE)/Drivers/BSP/P-NUCLEO-WB55.Nucleo/ -I$(STM32CUBE)/Drivers/CMSIS/Device/ST/STM32WBxx/Include \
-          -I$(STM32CUBE)/Drivers/STM32WBxx_HAL_Driver/Inc/ \
-          -I$(STM32CUBE)/Drivers/CMSIS/Include \
-          -Ihal \
-          -DSTM32WB55xx
+      PKA_EXTRA_OBJS+= $(STM32CUBE)/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pka.o $(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/port/st/stm32.o
+      PKA_EXTRA_CFLAGS+=-DWOLFSSL_STM32WB -DWOLFSSL_STM32_PKA -DWOLFSSL_STM32_CUBEMX -DNO_STM32_HASH -DSTM32WB55xx
+      PKA_EXTRA_CFLAGS+=-Isrc -Ihal \
+          -I$(STM32CUBE)/Drivers/STM32WBxx_HAL_Driver/Inc \
+          -I$(STM32CUBE)/Drivers/BSP/P-NUCLEO-WB55.Nucleo/ \
+          -I$(STM32CUBE)/Drivers/CMSIS/Device/ST/STM32WBxx/Include \
+          -I$(STM32CUBE)/Drivers/STM32WBxx_HAL_Driver/Inc \
+          -I$(STM32CUBE)/Drivers/CMSIS/Include
     endif
   endif
 
diff --git a/config/examples/stm32l4-cube.config b/config/examples/stm32l4-cube.config
@@ -15,7 +15,7 @@ SPMATH?=1
 RAM_CODE?=0
 DUALBANK_SWAP?=0
 IMAGE_HEADER_SIZE?=0x200
-STM32CUBE?=$(HOME)/STM32Cube/Repository/STM32Cube_FW_L4_V1.17.0
+STM32CUBE?=$(HOME)/STM32Cube/Repository/STM32Cube_FW_L4_V1.18.1
 WOLFBOOT_SECTOR_SIZE=0x1000
 WOLFBOOT_PARTITION_SIZE=0x7A000
 WOLFBOOT_PARTITION_BOOT_ADDRESS=0x0800A000
diff --git a/config/examples/stm32wb-pka-1mb.config b/config/examples/stm32wb-pka-1mb.config
@@ -8,3 +8,5 @@ WOLFBOOT_PARTITION_UPDATE_ADDRESS=0x08083800
 WOLFBOOT_PARTITION_SWAP_ADDRESS=0x080FF000
 NVM_FLASH_WRITEONCE=1
 PKA=1
+STM32CUBE?=$(HOME)/STM32Cube/Repository/STM32Cube_FW_WB_V1.23.0
+NO_ARM_ASM=1
diff --git a/hal/nrf5340.c b/hal/nrf5340.c
@@ -477,7 +477,6 @@ static uint32_t hal_shm_status_wait(ShmInfo_t* info, uint32_t status,
     uint32_t timeout_ms)
 {
     uint32_t status_ret = SHARED_STATUS_UNKNOWN;
-    int ret = 0;
 
     do {
         /* see if status shared already */
@@ -556,7 +555,7 @@ static void hal_net_check_version(void)
 {
     int ret;
     struct wolfBoot_image img;
-    uint32_t timeout, status = 0;
+    uint32_t status = 0;
 
 #ifdef TARGET_nrf5340_app
     /* check the network core version */
diff --git a/hal/pic32c.c b/hal/pic32c.c
@@ -376,8 +376,6 @@ void pic32_clock_pll0_init(int refdiv, int fbdiv, int bw, int postdiv)
 
 void pic32_clock_gclk_gen0(int mclk_div1, int cpudiv)
 {
-    uint32_t reg;
-
     /* setup clock division before changing the generator */
     if (mclk_div1 != 1)
         MCLK_DIV1 = mclk_div1;
diff --git a/hal/pic32cz.c b/hal/pic32cz.c
@@ -36,8 +36,6 @@
 
 static void pic32_supc_vreg_pll_enable(void)
 {
-    uint32_t reg;
-
     SUPC_VREGCTRL |= SUPC_VREGCTRL_AVREGEN_PLLREG_EN
         << SUPC_VREGCTRL_AVREGEN_SHIFT;
 
diff --git a/hal/sama5d3.c b/hal/sama5d3.c
@@ -223,12 +223,10 @@ static void mac_init(void)
 
 static void ddr_init(void)
 {
-    uint32_t val;
     uint32_t rtr, md, cr, tpr0, tpr1, tpr2;
     uint32_t col, row, cas, bank;
     uint32_t cal;
     uint32_t ba_offset = 0;
-    uint32_t pmc_pcr;
     volatile uint32_t *dram_base = (volatile uint32_t *)DRAM_BASE;
 
     /* Step 1: Calculate register values
@@ -551,8 +549,6 @@ static int nand_device_read(uint32_t row_address, uint8_t *data, int mode)
 {
     uint32_t col_address = 0x00;
     uint32_t tot_len = 0;
-    uint32_t page_size = nand_flash.page_size;
-    uint32_t pages_per_device = nand_flash.pages_per_device;
     uint32_t i;
 
     if (mode == NAND_MODE_DATAPAGE) {
@@ -668,8 +664,6 @@ int ext_flash_read(uintptr_t address, uint8_t *data, int len)
 
 static void pit_init(void)
 {
-    uint32_t pmc_pcr;
-
     /* Turn on clock for PIT */
     PMC_CLOCK_EN(PIT_PMCID);
 
diff --git a/hal/spi/spi_drv_stm32.c b/hal/spi/spi_drv_stm32.c
@@ -378,7 +378,6 @@ uint8_t RAMFUNCTION spi_read(void)
 
 void RAMFUNCTION spi_write(const char byte)
 {
-    int i;
     volatile uint32_t reg;
     do {
         reg = SPI1_SR;
diff --git a/hal/stm32_tz.c b/hal/stm32_tz.c
@@ -79,6 +79,7 @@ static int is_range_nonsecure(uint32_t address, int len)
     uint32_t min2 = WOLFBOOT_PARTITION_UPDATE_ADDRESS;
     uint32_t max2 = FLASH_TOP + 1;
     uint32_t end;
+    (void)boot_offset; /* calculated for reference, but not used */
     if (len < 0)
         return 0;
     end = (uint32_t)(address + len);
@@ -293,7 +294,6 @@ void hal_gtzc_init(void)
 
 void hal_tz_sau_init(void)
 {
-    uint32_t page_n = 0;
     /* SAU is set up before staging. Set up all areas as secure. */
 
     /* Non-secure callable: NSC functions area */
diff --git a/hal/stm32c0.c b/hal/stm32c0.c
@@ -195,7 +195,6 @@ void RAMFUNCTION hal_flash_lock(void)
 
 int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
 {
-    int start = -1, end = -1;
     uint32_t end_address;
     uint32_t p;
     if (len == 0)
diff --git a/hal/stm32f7.c b/hal/stm32f7.c
@@ -245,7 +245,6 @@ static void RAMFUNCTION clear_errors(void)
 int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
 {
     int i;
-    uint32_t val;
     flash_wait_complete();
     clear_errors();
     /* Set 8-bit write */
@@ -456,17 +455,17 @@ static uint8_t bootloader_copy_mem[BOOTLOADER_SIZE];
 
 void RAMFUNCTION fork_bootloader(void)
 {
-    uint8_t *data = (uint8_t *) WOLFBOOT_ORIG_BOOTLOADER;
-    uint32_t dst  = WOLFBOOT_COPY_BOOTLOADER;
-    uint32_t r = 0, w = 0;
     int i;
 
     /* Return if content already matches */
-    if (memcmp(data, (void *)WOLFBOOT_COPY_BOOTLOADER, BOOTLOADER_SIZE) == 0)
+    if (memcmp((void*)WOLFBOOT_ORIG_BOOTLOADER, (void*)WOLFBOOT_COPY_BOOTLOADER,
+            BOOTLOADER_SIZE) == 0) {
         return;
+    }
 
     /* Read the wolfBoot image in RAM */
-    memcpy(bootloader_copy_mem, data, BOOTLOADER_SIZE);
+    memcpy(bootloader_copy_mem, (void*)WOLFBOOT_ORIG_BOOTLOADER,
+        BOOTLOADER_SIZE);
 
     /* Disable ART pre-fetcher */
     FLASH_ACR &= ~(FLASH_ACR_PRFEN | FLASH_ACR_ARTEN);
diff --git a/hal/stm32g0.c b/hal/stm32g0.c
@@ -179,7 +179,6 @@ void RAMFUNCTION hal_flash_lock(void)
 
 int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
 {
-    int start = -1, end = -1;
     uint32_t end_address;
     uint32_t p;
     if (len == 0)
diff --git a/hal/stm32h5.c b/hal/stm32h5.c
@@ -100,8 +100,6 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
     int i = 0;
     uint32_t *src, *dst;
     uint32_t dword[2];
-    uint32_t off = 0;
-    uint32_t una_len = 0;
 
     hal_flash_clear_errors(0);
     src = (uint32_t *)data;
@@ -245,8 +243,6 @@ int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
 
 static void clock_pll_off(void)
 {
-    uint32_t reg32;
-
     /* Select HSI as SYSCLK source. */
     RCC_CFGR1 &= ~(0x07 << RCC_CFGR1_SW_SHIFT);
     DMB();
@@ -426,7 +422,6 @@ static void clock_pll_on(void)
 
 static void periph_unsecure(void)
 {
-    uint32_t pin;
     volatile uint32_t reg;
     volatile uint32_t *nvic_itns;
     uint32_t nvic_reg_pos, nvic_reg_off;
@@ -489,7 +484,7 @@ static void periph_unsecure(void)
 
 
 }
-#endif
+#endif /* TZ_SECURE() */
 
 
 #define AIRCR *(volatile uint32_t *)(0xE000ED0C)
@@ -550,7 +545,6 @@ static void fork_bootloader(void)
 {
     uint32_t data = (uint32_t) FLASHMEM_ADDRESS_SPACE;
     uint32_t dst  = FLASH_BANK2_BASE;
-    uint32_t r = 0, w = 0;
     int i;
 
 
@@ -649,9 +643,7 @@ int hal_flash_otp_write(uint32_t flashAddress, const void* data, uint16_t length
 {
     volatile uint16_t tmp_msw, tmp_lsw;
     uint16_t *pdata = (uint16_t *)data;
-    uint16_t idx = 0, len_align;
-    uint16_t last_word;
-    uint32_t blr_bitmap = 0;
+    uint16_t idx = 0;
     if (!(flashAddress >= FLASH_OTP_BASE && flashAddress <= FLASH_OTP_END)) {
         return -1;
     }
diff --git a/hal/stm32h7.c b/hal/stm32h7.c
@@ -90,8 +90,8 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
     uint32_t *src, *dst;
     uint8_t bank=0;
     uint8_t *vbytes = (uint8_t *)(stm32h7_cache);
-    int off = (address + i) - (((address + i) >> 5) << 5);
-    uint32_t base_addr = (address + i) & (~0x1F); /* aligned to 256 bit */
+    int off;
+    uint32_t base_addr;
 
     if ((address & FLASH_BANK2_BASE_REL) != 0) {
         bank = 1;
@@ -114,8 +114,8 @@ int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
             i+=32;
         }
         else {
-            int off = (address + i) - (((address + i) >> 5) << 5);
-            uint32_t base_addr = (address + i) & (~0x1F); /* aligned to 256 bit */
+            off = (address + i) - (((address + i) >> 5) << 5);
+            base_addr = (address + i) & (~0x1F); /* aligned to 256 bit */
             dst = (uint32_t *)(base_addr);
             for (ii = 0; ii < 8; ii++) {
                 stm32h7_cache[ii] = dst[ii];
@@ -359,7 +359,7 @@ static void clock_pll_off(void)
 static void clock_pll_on(int powersave)
 {
     uint32_t reg32;
-    uint32_t cpu_freq, plln, pllm, pllq, pllp, pllr, hpre, d1cpre, d1ppre;
+    uint32_t plln, pllm, pllq, pllp, pllr, hpre, d1cpre, d1ppre;
     uint32_t d2ppre1, d2ppre2, d3ppre, flash_waitstates;
 
     PWR_CR3 |= PWR_CR3_LDOEN;
diff --git a/hal/stm32l0.c b/hal/stm32l0.c
@@ -155,7 +155,6 @@ void RAMFUNCTION hal_flash_lock(void)
 
 int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
 {
-    int start = -1, end = -1;
     uint32_t end_address;
     uint32_t p;
     if (len == 0)
diff --git a/hal/stm32l5.c b/hal/stm32l5.c
@@ -308,8 +308,6 @@ static void clock_pll_on(int powersave)
 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
 static void periph_unsecure()
 {
-    uint32_t pin;
-
     /*Enable clock for User LED GPIOs */
     RCC_AHB2_CLOCK_ER|= LED_AHB2_ENABLE;
 
@@ -373,8 +371,6 @@ static void RAMFUNCTION fork_bootloader(void)
 {
     uint8_t *data = (uint8_t *) FLASHMEM_ADDRESS_SPACE;
     uint32_t dst  = FLASH_BANK2_BASE;
-    uint32_t r = 0, w = 0;
-    int i;
 
     /* Return if content already matches */
     if (memcmp(data, (void *)FLASH_BANK2_BASE, BOOTLOADER_SIZE) == 0)
diff --git a/hal/stm32u5.c b/hal/stm32u5.c
@@ -471,8 +471,6 @@ void RAMFUNCTION hal_flash_dualbank_swap(void)
 
 static void led_unsecure()
 {
-    uint32_t pin;
-
     /* Enable clock for User LED GPIOs */
     RCC_AHB2ENR1_CLOCK_ER|= GPIOH_AHB2ENR1_CLOCK_ER;
 
@@ -487,8 +485,6 @@ static void RAMFUNCTION fork_bootloader(void)
 {
     uint8_t *data = (uint8_t *) FLASHMEM_ADDRESS_SPACE;
     uint32_t dst  = FLASH_BANK2_BASE;
-    uint32_t r = 0, w = 0;
-    int i;
 
     /* Return if content already matches */
     if (memcmp(data, (void *)FLASH_BANK2_BASE, BOOTLOADER_SIZE) == 0)
diff --git a/hal/stm32wb.c b/hal/stm32wb.c
@@ -21,6 +21,11 @@
 
 #include <stdint.h>
 #include "image.h"
+
+#ifndef __WOLFBOOT
+#undef WOLFSSL_STM32_PKA
+#endif
+
 #ifdef WOLFSSL_STM32_PKA
 #include "stm32wbxx_hal.h"
 PKA_HandleTypeDef hpka = { };
@@ -49,7 +54,7 @@ PKA_HandleTypeDef hpka = { };
 #define RCC_CR_MSIRANGE_SHIFT        4
 #define RCC_CR_MSIRANGE_6            (0x06 << 4)
 #define RCC_CR_MSIRANGE_Msk          (0x0F << 4)
-#endif /* !WOLFSSL_STM32_PKA */
+#endif
 
 #define RCC_CFGR_SW_MSI               0x0
 #define RCC_CFGR_SW_PLL               0x3
@@ -250,7 +255,7 @@ static void clock_pll_off(void)
 static void clock_pll_on(void)
 {
     uint32_t reg32;
-    uint32_t cpu_freq, pllm, plln, pllp,pllq, pllr;
+    uint32_t cpu_freq;
     uint32_t hpre, ppre1, ppre2;
     uint32_t flash_waitstates;
 
@@ -313,7 +318,7 @@ static void clock_pll_on(void)
 void hal_init(void)
 {
     clock_pll_on();
-#ifdef WOLFSSL_STM32_PKA
+#if defined(__WOLFBOOT) && defined(WOLFSSL_STM32_PKA)
     __HAL_RCC_PKA_CLK_ENABLE();
     hpka.Instance = PKA;
     HAL_PKA_Init(&hpka);
diff --git a/hal/uart/uart_drv_stm32wb.c b/hal/uart/uart_drv_stm32wb.c
@@ -104,7 +104,6 @@ int uart_rx(uint8_t *c)
 
 int uart_init(uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
 {
-    uint32_t reg;
     /* Enable pins and configure for AF7 */
     uart_pins_setup();
 
diff --git a/include/user_settings.h b/include/user_settings.h
@@ -586,4 +586,8 @@ extern int tolower(int c);
 #   define WOLFSSL_PEM_TO_DER
 #endif
 
+#ifdef WOLFSSL_STM32_PKA
+#define HAVE_UINTPTR_T /* make sure stdint.h is included */
+#endif
+
 #endif /* !_WOLFBOOT_USER_SETTINGS_H_ */
diff --git a/src/boot_arm.c b/src/boot_arm.c
@@ -39,7 +39,9 @@ extern void main(void);
 
 #ifndef WOLFBOOT_NO_MPU
 
+#ifndef MPU_BASE
 #define MPU_BASE (0xE000ED90)
+#endif
 #define MPU_TYPE            *((volatile uint32_t *)(MPU_BASE + 0x00))
 #define MPU_CTRL            *((volatile uint32_t *)(MPU_BASE + 0x04))
 #define MPU_RNR             *((volatile uint32_t *)(MPU_BASE + 0x08))
diff --git a/src/image.c b/src/image.c
diff --git a/src/libwolfboot.c b/src/libwolfboot.c
diff --git a/src/pkcs11_store.c b/src/pkcs11_store.c
diff --git a/src/qspi_flash.c b/src/qspi_flash.c
diff --git a/src/update_flash.c b/src/update_flash.c

Original file line number	Diff line number	Diff line change
`@@ -477,7 +477,6 @@ static uint32_t hal_shm_status_wait(ShmInfo_t* info, uint32_t status,`
`477`	`477`	`uint32_t timeout_ms)`
`478`	`478`	`{`
`479`	`479`	`uint32_t status_ret = SHARED_STATUS_UNKNOWN;`
`480`		`- int ret = 0;`
`481`	`480`
`482`	`481`	`do {`
`483`	`482`	`/* see if status shared already */`
`@@ -556,7 +555,7 @@ static void hal_net_check_version(void)`
`556`	`555`	`{`
`557`	`556`	`int ret;`
`558`	`557`	`struct wolfBoot_image img;`
`559`		`- uint32_t timeout, status = 0;`
	`558`	`+ uint32_t status = 0;`
`560`	`559`
`561`	`560`	`#ifdef TARGET_nrf5340_app`
`562`	`561`	`/* check the network core version */`
Original file line number	Diff line number	Diff line change
`@@ -376,8 +376,6 @@ void pic32_clock_pll0_init(int refdiv, int fbdiv, int bw, int postdiv)`
`376`	`376`
`377`	`377`	`void pic32_clock_gclk_gen0(int mclk_div1, int cpudiv)`
`378`	`378`	`{`
`379`		`- uint32_t reg;`
`380`		`-`
`381`	`379`	`/* setup clock division before changing the generator */`
`382`	`380`	`if (mclk_div1 != 1)`
`383`	`381`	`MCLK_DIV1 = mclk_div1;`
Original file line number	Diff line number	Diff line change
`@@ -36,8 +36,6 @@`
`36`	`36`
`37`	`37`	`static void pic32_supc_vreg_pll_enable(void)`
`38`	`38`	`{`
`39`		`- uint32_t reg;`
`40`		`-`
`41`	`39`	`SUPC_VREGCTRL \|= SUPC_VREGCTRL_AVREGEN_PLLREG_EN`
`42`	`40`	`<< SUPC_VREGCTRL_AVREGEN_SHIFT;`
`43`	`41`
Original file line number	Diff line number	Diff line change
`@@ -378,7 +378,6 @@ uint8_t RAMFUNCTION spi_read(void)`
`378`	`378`
`379`	`379`	`void RAMFUNCTION spi_write(const char byte)`
`380`	`380`	`{`
`381`		`- int i;`
`382`	`381`	`volatile uint32_t reg;`
`383`	`382`	`do {`
`384`	`383`	`reg = SPI1_SR;`