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dgarskedanielinux
dgarske
authored and
danielinux
committed
Added STM32H5 SPI Driver and support for TPM
Cleanup STM32H5 HAL port. Refactor `__ARM_FEATURE_CMSE` to `TZ_SECURE()` Refactor attribute cmse_nonsecure_entry to use new macro `CSME_NSE_API` Added TPM Non Secure Callable API's Added TPM support to STM32H5 test application
1 parent ecf1cb8 commit 8cb3d33

30 files changed

+1119
-409
lines changed

‎.github/workflows/test-configs.yml‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -320,6 +320,12 @@ jobs:
320320
arch: arm
321321
config-file: ./config/examples/stm32h5-tz.config
322322

323+
stm32h5_tz_tpm_test:
324+
uses: ./.github/workflows/test-build.yml
325+
with:
326+
arch: arm
327+
config-file: ./config/examples/stm32h5-tz-tpm.config
328+
323329
stm32h5_tz_dualbank_test:
324330
uses: ./.github/workflows/test-build.yml
325331
with:

‎Makefile‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -105,7 +105,7 @@ CFLAGS+= \
105105
# Setup default optimizations (for GCC)
106106
ifeq ($(USE_GCC_HEADLESS),1)
107107
CFLAGS+=-Wall -Wextra -Wno-main -ffreestanding -Wno-unused -nostartfiles
108-
CFLAGS+=-ffunction-sections -fdata-sections -fomit-frame-pointer
108+
CFLAGS+=-ffunction-sections -fdata-sections -fomit-frame-pointer -Wno-unused-variable
109109
LDFLAGS+=-Wl,-gc-sections -Wl,-Map=wolfboot.map -ffreestanding -nostartfiles
110110
# Not setting LDFLAGS directly since it is passed to the test-app
111111
LSCRIPT_FLAGS+=-T $(LSCRIPT)
@@ -531,6 +531,8 @@ cppcheck:
531531
cppcheck -f --enable=warning --enable=portability \
532532
--suppress="ctunullpointer" --suppress="nullPointer" \
533533
--suppress="objectIndex" --suppress="comparePointers" \
534+
--suppress="subtractPointers" --suppress="intToPointerCast" \
535+
--check-level=exhaustive \
534536
--error-exitcode=89 --std=c89 src/*.c hal/*.c hal/spi/*.c hal/uart/*.c
535537

536538
otp: tools/keytools/otp/otp-keystore-primer.bin FORCE

‎arch.mk‎

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -101,7 +101,7 @@ ifeq ($(ARCH),AARCH64)
101101
MATH_OBJS += $(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/sp_c32.o
102102
MATH_OBJS += $(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/sp_arm64.o
103103
endif
104-
ifeq ($(NO_ARM_ASM),0)
104+
ifneq ($(NO_ARM_ASM),1)
105105
ARCH_FLAGS=-mstrict-align
106106
CFLAGS+=$(ARCH_FLAGS) -DWOLFSSL_ARMASM -DWOLFSSL_ARMASM_INLINE -DWC_HASH_DATA_ALIGNMENT=8 -DWOLFSSL_AARCH64_PRIVILEGE_MODE
107107
WOLFCRYPT_OBJS += $(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/cpuid.o \
@@ -250,7 +250,6 @@ ifeq ($(ARCH),ARM)
250250
WOLFBOOT_ORIGIN=0x10000000
251251
ifeq ($(TZEN),1)
252252
LSCRIPT_IN=hal/$(TARGET).ld
253-
CFLAGS+=-DTZEN
254253
else
255254
LSCRIPT_IN=hal/$(TARGET)-ns.ld
256255
endif
@@ -323,7 +322,6 @@ else
323322
$(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/port/arm/thumb2-chacha-asm.o \
324323
$(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src/port/arm/thumb2-chacha-asm_c.o
325324

326-
327325
CORTEXM_ARM_EXTRA_CFLAGS+=-DWOLFSSL_ARMASM -DWOLFSSL_ARMASM_NO_HW_CRYPTO \
328326
-DWOLFSSL_ARMASM_NO_NEON -DWOLFSSL_ARMASM_THUMB2
329327
endif
@@ -420,10 +418,6 @@ endif
420418
endif
421419
endif
422420

423-
ifeq ($(TZEN),1)
424-
CFLAGS+=-DTZEN
425-
endif
426-
427421

428422
## Renesas RX
429423
ifeq ($(ARCH),RENESAS_RX)

‎config/examples/stm32h5-tz-tpm.config‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
1+
ARCH?=ARM
2+
TZEN?=1
3+
TARGET?=stm32h5
4+
SIGN?=ECC256
5+
HASH?=SHA256
6+
DEBUG?=0
7+
VTOR?=1
8+
CORTEX_M0?=0
9+
CORTEX_M33?=1
10+
NO_ASM?=0
11+
NO_MPU=1
12+
EXT_FLASH?=0
13+
SPI_FLASH?=0
14+
ALLOW_DOWNGRADE?=0
15+
NVM_FLASH_WRITEONCE?=1
16+
WOLFBOOT_VERSION?=1
17+
V?=0
18+
SPMATH?=1
19+
RAM_CODE?=1
20+
DUALBANK_SWAP?=0
21+
WOLFBOOT_PARTITION_SIZE?=0xA0000
22+
WOLFBOOT_SECTOR_SIZE?=0x2000
23+
WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08060000
24+
WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x0C100000
25+
WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x0C1A0000
26+
FLAGS_HOME=0
27+
DISABLE_BACKUP=0
28+
WOLFCRYPT_TZ=1
29+
WOLFCRYPT_TZ_PKCS11=1
30+
IMAGE_HEADER_SIZE?=1024
31+
ARMORED=1
32+
WOLFTPM=1

‎hal/spi/spi_drv_stm32.c‎

Lines changed: 51 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -83,6 +83,8 @@ void RAMFUNCTION stm_gpio_config(uint32_t base, uint32_t pin, uint32_t mode,
8383

8484
/* Enable GPIO clock */
8585
RCC_GPIO_CLOCK_ER |= (1 << base_num);
86+
/* Delay after an RCC peripheral clock enabling */
87+
reg = RCC_GPIO_CLOCK_ER;
8688

8789
/* Set Mode and Alternate Function */
8890
reg = GPIO_MODE(base) & ~(0x03UL << (pin * 2));
@@ -112,6 +114,10 @@ void RAMFUNCTION stm_gpio_config(uint32_t base, uint32_t pin, uint32_t mode,
112114
/* configure output speed 0=low, 1=med, 2=high, 3=very high */
113115
reg = GPIO_OSPD(base) & ~(0x03UL << (pin * 2));
114116
GPIO_OSPD(base) |= (speed << (pin * 2));
117+
118+
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
119+
/* TODO: Consider setting GPIO_SECCFGR(base) */
120+
#endif
115121
}
116122

117123
#if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
@@ -369,24 +375,14 @@ int qspi_transfer(uint8_t fmode, const uint8_t cmd,
369375
#if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
370376
uint8_t RAMFUNCTION spi_read(void)
371377
{
372-
volatile uint32_t reg;
373-
do {
374-
reg = SPI1_SR;
375-
} while(!(reg & SPI_SR_RX_NOTEMPTY));
376-
return (uint8_t)SPI1_DR;
378+
while (!(SPI1_SR & SPI_SR_RX_NOTEMPTY));
379+
return SPI1_RXDR;
377380
}
378381

379382
void RAMFUNCTION spi_write(const char byte)
380383
{
381-
int i;
382-
volatile uint32_t reg;
383-
do {
384-
reg = SPI1_SR;
385-
} while ((reg & SPI_SR_TX_EMPTY) == 0);
386-
SPI1_DR = byte;
387-
do {
388-
reg = SPI1_SR;
389-
} while ((reg & SPI_SR_TX_EMPTY) == 0);
384+
while (!(SPI1_SR & SPI_SR_TX_EMPTY));
385+
SPI1_TXDR = (uint8_t)byte;
390386
}
391387
#endif /* SPI_FLASH || WOLFBOOT_TPM */
392388

@@ -398,7 +394,6 @@ void RAMFUNCTION spi_init(int polarity, int phase)
398394

399395
/* Setup clocks */
400396
#if defined(QSPI_FLASH) || defined(OCTOSPI_FLASH)
401-
402397
#ifdef TARGET_stm32u5
403398
/* Clock configuration for QSPI defaults to SYSCLK
404399
* (RM0456 section 11.8.47)
@@ -413,6 +408,10 @@ void RAMFUNCTION spi_init(int polarity, int phase)
413408

414409
#if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
415410
APB2_CLOCK_ER |= SPI1_APB2_CLOCK_ER_VAL;
411+
#ifdef TARGET_stm32h5
412+
RCC_CCIPR3 &= ~ (RCC_CCIPR3_SPI1SEL_MASK << RCC_CCIPR3_SPI1SEL_SHIFT);
413+
RCC_CCIPR3 |= (0 << RCC_CCIPR3_SPI1SEL_SHIFT); /* PLL1_Q */
414+
#endif
416415
#endif
417416

418417
/* reset peripheral before setting up GPIO pins */
@@ -486,14 +485,39 @@ void RAMFUNCTION spi_init(int polarity, int phase)
486485
#endif
487486
#if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
488487
/* Configure SPI1 for master mode */
489-
# ifdef TARGET_stm32l0
490-
SPI1_CR1 = SPI_CR1_MASTER | (polarity << 1) | (phase << 0);
491-
# else
492-
/* baud rate 5 (hclk/6) */
493-
SPI1_CR1 = SPI_CR1_MASTER | (5 << 3) | (polarity << 1) | (phase << 0);
494-
# endif
488+
SPI1_CR1 &= ~SPI_CR1_SPI_EN;
489+
#if defined(TARGET_stm32h5)
490+
/* Clear any faults in the status register */
491+
SPI1_IFCR = (SPI_IFCR_SUSPC | SPI_IFCR_MODFC | SPI_IFCR_TIFREC |
492+
SPI_IFCR_OVRC | SPI_IFCR_UDRC);
493+
494+
/* baud rate 2 (hclk/8), data size (8-bits), CRC Size (8-bits),
495+
* FIFO threshold level (1-data) */
496+
SPI1_CFG1 = (
497+
((2 & SPI_CFG1_BAUDRATE_MASK) << SPI_CFG1_BAUDRATE_SHIFT) |
498+
((7 & SPI_CFG1_CRCSIZE_MASK) << SPI_CFG1_CRCSIZE_SHIFT) |
499+
((0 & SPI_CFG1_FTHLV_MASK) << SPI_CFG1_FTHLV_SHIFT) |
500+
((7 & SPI_CFG1_DSIZE_MASK) << SPI_CFG1_DSIZE_SHIFT));
501+
SPI1_CFG2 = SPI_CFG2_MASTER | SPI_CFG2_SSOE |
502+
(polarity << SPI_CFG2_CLOCK_POL_SHIFT) |
503+
(phase << SPI_CFG2_CLOCK_PHASE_SHIFT);
504+
#else
505+
#ifndef TARGET_stm32l0 /* use existing/default baud for L0 */
506+
/* Baud rate 5 (hclk/6), data size 8 bits */
507+
SPI1_CR1 |= ((5 & SPI_CR1_BAUDRATE_MASK) << SPI_CR1_BAUDRATE_SHIFT);
508+
#endif
509+
SPI1_CR1 &= ~((1 << SPI_CR1_CLOCK_POL_SHIFT) | (1 << SPI_CR1_CLOCK_PHASE_SHIFT));
510+
SPI1_CR1 |= SPI_CR1_MASTER |
511+
(polarity << SPI_CR1_CLOCK_POL_SHIFT) |
512+
(phase << SPI_CR1_CLOCK_PHASE_SHIFT);
495513
SPI1_CR2 |= SPI_CR2_SSOE;
496-
SPI1_CR1 |= SPI_CR1_SPI_EN;
514+
#endif
515+
516+
SPI1_CR1 |= SPI_CR1_SPI_EN; /* Enable SPI */
517+
518+
#ifdef SPI_CR1_CSTART
519+
SPI1_CR1 |= SPI_CR1_CSTART; /* use continuous start mode */
520+
#endif
497521
#endif /* SPI_FLASH || WOLFBOOOT_TPM */
498522
}
499523
}
@@ -505,8 +529,12 @@ void RAMFUNCTION spi_release(void)
505529
}
506530
if (initialized == 0) {
507531
spi_reset();
508-
#if defined (SPI_FLASH) || defined(WOLFBOOT_TPM)
532+
#if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
533+
#if defined(TARGET_stm32h5)
534+
SPI1_CFG2 &= ~SPI_CFG2_SSOE;
535+
#else
509536
SPI1_CR2 &= ~SPI_CR2_SSOE;
537+
#endif
510538
SPI1_CR1 = 0;
511539
#endif
512540
stm_pins_release();

‎hal/spi/spi_drv_stm32.h‎

Lines changed: 82 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,6 @@
2929
#define GPIOC_BASE (0x40020800)
3030
#define GPIOD_BASE (0x40020C00)
3131
#define GPIOE_BASE (0x40021000)
32-
#define GPIO_BASE GPIOA_BASE
3332
#define SPI_GPIO GPIOB_BASE
3433
#define SPI_CS_GPIO GPIOE_BASE
3534
#define SPI_CS_FLASH 1 /* Flash CS connected to GPIOE1 */
@@ -40,6 +39,28 @@
4039
#define SPI_MOSI_PIN 5 /* SPI_MOSI PB5 */
4140
#endif /* TARGET_stm32f4 */
4241

42+
43+
#ifdef TARGET_stm32h5
44+
#include "hal/stm32h5.h"
45+
46+
#define APB2_CLOCK_RST RCC_APB2_CLOCK_RSTR
47+
#define APB2_CLOCK_ER RCC_APB2_CLOCK_ER
48+
#define RCC_GPIO_CLOCK_ER RCC_AHB2ENR_CLOCK_ER
49+
50+
/* Nucleo STM32H573ZI SPI_A Port (SPI1) */
51+
#define SPI_CLOCK_PIO_BASE GPIOA_BASE
52+
#define SPI_MISO_PIO_BASE GPIOG_BASE
53+
#define SPI_MOSI_PIO_BASE GPIOB_BASE
54+
#define SPI_CS_TPM_PIO_BASE GPIOD_BASE
55+
56+
#define SPI_PIN_AF 5 /* Alternate function for SPI pins */
57+
#define SPI_CLOCK_PIN 5 /* SPI_SCK: PA5 */
58+
#define SPI_MISO_PIN 9 /* SPI_MISO PG9 */
59+
#define SPI_MOSI_PIN 5 /* SPI_MOSI PB5 */
60+
#define SPI_CS_TPM 14 /* TPM CS connected to PD14 */
61+
#endif /* TARGET_stm32h5 */
62+
63+
4364
#ifdef TARGET_stm32u5
4465

4566
#ifdef TZEN
@@ -405,15 +426,67 @@
405426

406427
#define SPI1_APB2_CLOCK_ER_VAL (1 << 12)
407428

429+
#if defined(TARGET_stm32h5)
430+
/* newer SPI/I2S peripheral */
431+
#define SPI1_CR1 (*(volatile uint32_t *)(SPI1_BASE))
432+
#define SPI1_CR2 (*(volatile uint32_t *)(SPI1_BASE + 0x04))
433+
#define SPI1_CFG1 (*(volatile uint32_t *)(SPI1_BASE + 0x08))
434+
#define SPI1_CFG2 (*(volatile uint32_t *)(SPI1_BASE + 0x0C))
435+
#define SPI1_SR (*(volatile uint32_t *)(SPI1_BASE + 0x14))
436+
#define SPI1_IFCR (*(volatile uint32_t *)(SPI1_BASE + 0x18))
437+
#define SPI1_TXDR (*(volatile uint8_t *)(SPI1_BASE + 0x20))
438+
#define SPI1_RXDR (*(volatile uint8_t *)(SPI1_BASE + 0x30))
439+
440+
#define SPI_CR1_SPI_EN (1 << 0)
441+
#define SPI_CR1_MASRX (1 << 8) /* master automatic suspension in Receive mode */
442+
#define SPI_CR1_CSTART (1 << 9) /* Continous start */
443+
#define SPI_CR1_SSI (1 << 12) /* Internal slave select signal input level */
444+
#define SPI_CFG1_DSIZE_MASK (0x1F)
445+
#define SPI_CFG1_DSIZE_SHIFT (0)
446+
#define SPI_CFG1_FTHLV_MASK (0x1F)
447+
#define SPI_CFG1_FTHLV_SHIFT (5)
448+
#define SPI_CFG1_CRCSIZE_MASK (0x1F)
449+
#define SPI_CFG1_CRCSIZE_SHIFT (16)
450+
#define SPI_CFG1_BAUDRATE_MASK (0x07)
451+
#define SPI_CFG1_BAUDRATE_SHIFT (28)
452+
453+
#define SPI_CFG2_MASTER (1 << 22)
454+
#define SPI_CFG2_LSBFIRST (1 << 23)
455+
#define SPI_CFG2_CLOCK_PHASE_SHIFT (24)
456+
#define SPI_CFG2_CLOCK_POL_SHIFT (25)
457+
#define SPI_CFG2_SSM (1 << 26)
458+
#define SPI_CFG2_SSOE (1 << 29)
459+
#define SPI_CFG2_SSOM (1 << 30)
460+
#define SPI_CFG2_AFCNTR (1 << 31) /* alternate function GPIOs control */
461+
#define SPI_CFG2_COMM_MASK (0x3) /* 0=full duplex, 1=simplex tx, 2=simplex rx, 3=half duplex */
462+
#define SPI_CFG2_COMM_SHIFT (17)
463+
464+
#define SPI_IFCR_SUSPC (1 << 11)
465+
#define SPI_IFCR_MODFC (1 << 9)
466+
#define SPI_IFCR_TIFREC (1 << 8)
467+
#define SPI_IFCR_CRCEC (1 << 7)
468+
#define SPI_IFCR_OVRC (1 << 6)
469+
#define SPI_IFCR_UDRC (1 << 5)
470+
#define SPI_IFCR_TXTFC (1 << 4)
471+
#define SPI_IFCR_EOTC (1 << 3)
472+
473+
#define SPI_SR_RX_NOTEMPTY (1 << 0)
474+
#define SPI_SR_TX_EMPTY (1 << 1)
475+
476+
#else
477+
478+
/* older SPI peripheral */
408479
#define SPI1_CR1 (*(volatile uint32_t *)(SPI1_BASE))
409480
#define SPI1_CR2 (*(volatile uint32_t *)(SPI1_BASE + 0x04))
410481
#define SPI1_SR (*(volatile uint32_t *)(SPI1_BASE + 0x08))
411-
#define SPI1_DR (*(volatile uint32_t *)(SPI1_BASE + 0x0c))
482+
#define SPI1_TXDR (*(volatile uint8_t *)(SPI1_BASE + 0x0c))
483+
#define SPI1_RXDR (*(volatile uint8_t *)(SPI1_BASE + 0x0c))
412484

413-
#define SPI_CR1_CLOCK_PHASE (1 << 0)
414-
#define SPI_CR1_CLOCK_POLARITY (1 << 1)
485+
#define SPI_CR1_CLOCK_PHASE_SHIFT (0)
486+
#define SPI_CR1_CLOCK_POL_SHIFT (1)
415487
#define SPI_CR1_MASTER (1 << 2)
416-
#define SPI_CR1_BAUDRATE (0x07 << 3)
488+
#define SPI_CR1_BAUDRATE_MASK (0x07)
489+
#define SPI_CR1_BAUDRATE_SHIFT (3)
417490
#define SPI_CR1_SPI_EN (1 << 6)
418491
#define SPI_CR1_LSBFIRST (1 << 7)
419492
#define SPI_CR1_SSI (1 << 8)
@@ -428,6 +501,7 @@
428501
#define SPI_SR_TX_EMPTY (1 << 1)
429502
#define SPI_SR_BUSY (1 << 7)
430503

504+
#endif
431505

432506
/* GPIO */
433507
#define GPIO_MODE(base) (*(volatile uint32_t *)(base + 0x00)) /* GPIOx_MODER */
@@ -438,6 +512,9 @@
438512
#define GPIO_BSRR(base) (*(volatile uint32_t *)(base + 0x18)) /* GPIOx_BSRR */
439513
#define GPIO_AFL(base) (*(volatile uint32_t *)(base + 0x20)) /* GPIOx_AFRL */
440514
#define GPIO_AFH(base) (*(volatile uint32_t *)(base + 0x24)) /* GPIOx_AFRH */
515+
#ifndef GPIO_SECCFGR
516+
#define GPIO_SECCFGR(base) (*(volatile uint32_t *)(base + 0x30)) /* GPIOx_SECCFGR */
517+
#endif
441518

442519
#define GPIO_MODE_INPUT (0)
443520
#define GPIO_MODE_OUTPUT (1)

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