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wolfBoot runs from DDR at address `0x8000000` at EL2 (non-secure). All clock, MIO, and DDR initialization is handled by PLM/PSM before wolfBoot starts.
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See example configuration file at `config/examples/versal_vmk180.config`.
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### Prerequisites
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1.**Xilinx Vitis 2024.1 or 2024.2** (required for bootgen - 2025.1 or later has QSPI boot issues)
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- Set `VITIS_PATH` environment variable: `export VITIS_PATH=/opt/Xilinx/Vitis/2024.1`
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2.**Toolchain**
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- ARM GCC toolchain: `aarch64-none-elf-gcc`
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### Configuration Options
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Key configuration options in `config/examples/versal_vmk180.config`:
The BIF file (`boot_wolfboot.bif`) references files using relative paths in the same directory. After successful generation, `BOOT.BIN` will be created in `tools/scripts/vmk180/`.
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### Flashing QSPI
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Flash `BOOT.BIN` to QSPI flash using one of the following methods:
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-**Vitis**: Use the Hardware Manager to program the QSPI flash via JTAG. Load `BOOT.BIN` and program to QSPI32 flash memory.
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-**Lauterbach**: Use Trace32 to program QSPI flash via JTAG. Load `BOOT.BIN` and write to QSPI flash memory addresses.
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-**U-Boot via SD Card**: Boot from SD card with U-Boot, then use TFTP to download `BOOT.BIN` and program QSPI flash:
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```sh
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tftp ${loadaddr} BOOT.BIN
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sf probe 0 0 0
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sf erase 0 +${filesize}
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sf write ${loadaddr} 0 ${filesize}
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```
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### Example Boot Output
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```
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========================================
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wolfBoot Secure Boot - AMD Versal
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========================================
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Current EL: 2
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Timer Freq: 99999904 Hz
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ext_flash_read: STUB
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ext_flash_read: STUB
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Versions: Boot 0, Update 0
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No valid image found!
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wolfBoot: PANIC!
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```
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## Cypress PSoC-6
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The Cypress PSoC 62S2 is a dual-core Cortex-M4 & Cortex-M0+ MCU. The secure boot process is managed by the M0+.
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