NXP T1024 wolfBoot support:

* Added DDR4 w/ECC.
* Added L2 and L2 CPC SRAM support
* Added platform SRAM 160KB support
* Added support for core timers (timebase) and platform clock.
* Added IFC driver with erase/write
* Added stage 1 loader to relocate wolfBoot to DDR
* Added CPLD, QUICC, FMAN and MP drivers
* Added eSPI driver for TPM.
* Added hal_early_init instead of calling ddr_init directly.
* Fixes for device tree (DTB) loading with update_ram and PPC boot.
* Fixes for relocating CCSRBAR to upper.
* Fixes for interrupt offsets.

Author: dgarske

.github/workflows/test-configs.yml

@@ -76,6 +76,12 @@ jobs:
       arch: ppc
       config-file: ./config/examples/nxp-p1021.config
 
+  nxp_t1024_test:
+    uses: ./.github/workflows/test-build.yml
+    with:
+      arch: ppc
+      config-file: ./config/examples/nxp-t1024.config
+
   nxp_t2080_68ppc2_test:
     uses: ./.github/workflows/test-build.yml
     with:

Makefile

@@ -106,6 +106,9 @@ endif
 ifeq ($(TARGET),nxp_p1021)
 	MAIN_TARGET:=factory_wstage1.bin
 endif
+ifeq ($(TARGET),nxp_t1024)
+	MAIN_TARGET:=factory_wstage1.bin
+endif
 
 ASFLAGS:=$(CFLAGS)
 BOOTLOADER_PARTITION_SIZE?=$$(( $(WOLFBOOT_PARTITION_BOOT_ADDRESS) - $(ARCH_FLASH_OFFSET)))

arch.mk

@@ -412,9 +412,30 @@ ifeq ($(ARCH),ARM_BE)
   endif
 endif
 
+ifeq ($(TARGET),nxp_t1024)
+  # Power PC big endian
+  ARCH_FLAGS=-mhard-float -mcpu=e5500
+  CFLAGS+=$(ARCH_FLAGS) -DBIG_ENDIAN_ORDER
+  CFLAGS+=-DMMU -DWOLFBOOT_DUALBOOT
+  CFLAGS+=-pipe # use pipes instead of temp files
+  CFLAGS+=-feliminate-unused-debug-types
+  LDFLAGS+=$(ARCH_FLAGS)
+  LDFLAGS+=-Wl,--hash-style=both # generate both sysv and gnu symbol hash table
+  LDFLAGS+=-Wl,--as-needed # remove weak functions not used
+  OBJS+=src/boot_ppc_mp.o # support for spin table
+  UPDATE_OBJS:=src/update_ram.o
+  ifeq ($(SPMATH),1)
+    MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
+  else
+    # Use the SP math all assembly accelerations
+    CFLAGS+=-DWOLFSSL_SP_PPC
+  endif
+  SPI_TARGET=nxp
+endif
+
 ifeq ($(TARGET),nxp_t2080)
   # Power PC big endian
-  ARCH_FLAGS=-m32 -mhard-float -mcpu=e6500
+  ARCH_FLAGS=-mhard-float -mcpu=e6500
   CFLAGS+=$(ARCH_FLAGS) -DBIG_ENDIAN_ORDER
   CFLAGS+=-DMMU -DWOLFBOOT_DUALBOOT
   CFLAGS+=-pipe # use pipes instead of temp files
@@ -440,8 +461,8 @@ ifeq ($(TARGET),nxp_p1021)
   CFLAGS+=-pipe # use pipes instead of temp files
   LDFLAGS+=$(ARCH_FLAGS)
   LDFLAGS+=-Wl,--as-needed # remove weak functions not used
+  OBJS+=src/boot_ppc_mp.o # support for spin table
   UPDATE_OBJS:=src/update_ram.o
-  UPDATE_OBJS+=src/boot_ppc_mp.o
 
   # Use PPC stdlib for memcpy, etc.
   #CFLAGS+=-DWOLFBOOT_USE_STDLIBC

config/examples/nxp-t1024.config

@@ -0,0 +1,67 @@
+# NXP QorIQ T1024 (2 core)
+
+ARCH=PPC
+TARGET=nxp_t1024
+SIGN?=ECC384
+HASH?=SHA384
+IMAGE_HEADER_SIZE?=512
+DEBUG?=0
+DEBUG_UART?=1
+VTOR?=1
+CORTEX_M0?=0
+NO_ASM?=0
+EXT_FLASH?=0
+SPI_FLASH?=0
+NO_XIP?=0
+UART_FLASH?=0
+ALLOW_DOWNGRADE?=0
+NVM_FLASH_WRITEONCE?=0
+WOLFBOOT_VERSION?=0
+NO_MPU?=0
+SPMATH?=0
+SPMATHALL?=1
+RAM_CODE?=0
+DUALBANK_SWAP?=0
+WOLFTPM?=0
+ELF?=1
+DEBUG_ELF=0
+
+# NOR Base Address
+ARCH_FLASH_OFFSET?=0xEC000000
+
+# Flash Sector Size
+WOLFBOOT_SECTOR_SIZE=0x10000
+
+# wolfBoot start address
+WOLFBOOT_ORIGIN=0xEFF40000
+# wolfBoot partition size (custom)
+BOOTLOADER_PARTITION_SIZE=0xC0000
+
+# Application Partition Size
+WOLFBOOT_PARTITION_SIZE?=0x01E00000
+# Location in Flash for Application Partition
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xEE000000
+# Load Partition to RAM Address
+WOLFBOOT_LOAD_ADDRESS?=0x70000000
+
+# Location in Flash for Update Partition
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0xEC200000
+
+# Location of temporary sector used during updates
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xEC0F0000
+
+# Stage 1 loader settings (16KB)
+WOLFBOOT_STAGE1_SIZE=0x4000
+# Location in Flash for stage 1 loader (XIP from boot ROM)
+WOLFBOOT_STAGE1_FLASH_ADDR=0xEFFFC000
+# Address in RAM to load wolfBoot (end of DDR at 2GB-1MB)
+WOLFBOOT_STAGE1_LOAD_ADDR=0x7FF00000
+
+# DTS (Device Tree)
+WOLFBOOT_DTS_BOOT_ADDRESS?=0xEC020000
+WOLFBOOT_DTS_UPDATE_ADDRESS?=0xEC040000
+# DTS Load to RAM Address
+WOLFBOOT_LOAD_DTS_ADDRESS?=0x7F100000
+
+# Load to RAM before hash and verify
+CFLAGS_EXTRA+=-DWOLFBOOT_USE_RAMBOOT

config/examples/nxp-t2080.config

@@ -30,7 +30,13 @@ ARCH_FLASH_OFFSET?=0xEFFF0000
 BOOTLOADER_PARTITION_SIZE=0x10000
 
 WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xEFFD0000
+WOLFBOOT_LOAD_ADDRESS?=0x19000
 WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0xEFFB0000
+
+# Location of temporary sector used during updates
 WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xEFFA0000
-WOLFBOOT_LOAD_ADDRESS?=0x200000
-WOLFBOOT_LOAD_DTS_ADDRESS?=0x40000
+
+# DTS (Device Tree)
+WOLFBOOT_DTS_BOOT_ADDRESS?=0xE8040000
+WOLFBOOT_DTS_UPDATE_ADDRESS?=0xE8050000
+WOLFBOOT_LOAD_DTS_ADDRESS?=0x200000

docs/Targets.md

@@ -11,6 +11,7 @@ This README describes configuration of supported targets.
 * [NXP iMX-RT](#nxp-imx-rt)
 * [NXP Kinetis](#nxp-kinetis)
 * [NXP P1021 PPC](#nxp-qoriq-p1021-ppc)
+* [NXP T1024 PPC](#nxp-qoriq-t1024-ppc)
 * [NXP T2080 PPC](#nxp-qoriq-t2080-ppc)
 * [Qemu x86-64 UEFI](#qemu-x86-64-uefi)
 * [SiFive HiFive1 RISC-V](#sifive-hifive1-risc-v)
@@ -1245,6 +1246,92 @@ make factory_wstage1.bin
 ```
 
 
+## NXP QorIQ T1024 PPC
+
+The NXP QorIQ T1024 is a two core 64-bit PPC e5500 based processor at 1400MHz. Each core has 256KB L2 cache.
+
+Board: T1024RDB
+Board rev: 0x3031
+CPLD ver: 0x42
+
+T1024E, Version: 1.0, (0x8548_0010)
+e5500, Version: 2.1, (0x8024_1021)
+
+Reset Configuration Word (RCW):
+00000000: 0810000e 00000000 00000000 00000000
+00000010: 2d800003 40408812 fc027000 21000000
+00000020: 00000000 00000000 60000000 00036800
+00000030: 00000100 484a5808 00000000 00000006
+
+Flash is NOR on IFC CS0 (0x0_EC00_0000) 64MB (default).
+
+Default NOR Flash Memory Layout (64MB):
+
+| Description       | Address    | Size                |
+| ----------------- | ---------- | ------------------- |
+| RCW               | 0xEC000000 | 0x00020000 (128 KB) |
+| Primary (FDT)     | 0xEC020000 | 0x00020000 (128 KB) |
+| Update (FDT)      | 0xEC040000 | 0x00020000 (128 KB) |
+| Free              | 0xEC060000 | 0x00090000 (576 KB) |
+| Swap Sector       | 0xEC0F0000 | 0x00010000 ( 64 KB) |
+| Free              | 0xEC100000 | 0x00100000 (  1 MB) |
+| Update (OS)       | 0xEC200000 | 0x01E00000 ( 30 MB) |
+| Application (OS)  | 0xEE000000 | 0x01E00000 ( 30 MB) |
+| QUICC             | 0xEFE00000 | 0x00100000 (  1 MB) |
+| DPAA (FMAN)       | 0xEFF00000 | 0x00020000 (128 KB) |
+| wolfBoot          | 0xEFF40000 | 0x000BC000 (752 KB) |
+| wolfBoot Stage 1  | 0xEFFFC000 | 0x00004000 ( 16 KB) |
+
+QE: uploading microcode 'Microcode for T1024 r1.0' version 0.0.1
+
+DDR4 2GB
+
+### Building wolfBoot for NXP T1024 PPC
+
+By default wolfBoot will use `powerpc-linux-gnu-` cross-compiler prefix. These tools can be installed with the Debian package `gcc-powerpc-linux-gnu` (`sudo apt install gcc-powerpc-linux-gnu`).
+
+The `make` creates a `factory_stage1.bin` image that can be programmed at `0xEC000000`
+
+```
+cp ./config/examples/nxp-t1024.config .config
+make clean
+make keytools
+make
+```
+
+Or each `make` component can be manually built using:
+
+```
+make stage1
+make wolfboot.elf
+make test-app/image_v1_signed.bin
+```
+
+If getting errors with keystore then you can reset things using `make distclean`.
+
+### Signing Custom application
+
+```
+./tools/keytools/sign --ecc384 --sha384 custom.elf wolfboot_signing_private_key.der 1
+```
+
+### Assembly of custom firmware image
+
+```
+./tools/bin-assemble/bin-assemble factory_custom.bin \
+    0xEC000000 RCW_CTS.bin \
+    0xEC020000 custom.dtb \
+    0xEE000000 custom_v1_signed.bin \
+    0xEFE00000 iram_Type_A_T1024_r1.0.bin \
+    0xEFF00000 fsl_fman_ucode_t1024_r1.0_108_4_5.bin \
+    0xEFF40000 wolfboot.bin \
+    0xEFFFC000 stage1/loader_stage1.bin
+```
+
+Flash factory_custom.bin to NOR base 0xEC00_0000
+
+
+
 ## NXP QorIQ T2080 PPC
 
 The NXP QorIQ T2080 is a PPC e6500 based processor (four cores). Support has been tested with the NAII 68PPC2.

hal/nxp_p1021.c

@@ -419,7 +419,6 @@ enum elbc_amask_sizes {
 #define DDR_SDRAM_MODE     ((volatile uint32_t*)(DDR_BASE + 0x118)) /* DDR SDRAM mode configuration */
 #define DDR_SDRAM_MODE_2   ((volatile uint32_t*)(DDR_BASE + 0x11C)) /* DDR SDRAM mode configuration 2 */
 #define DDR_SDRAM_MD_CNTL  ((volatile uint32_t*)(DDR_BASE + 0x120)) /* DDR SDRAM mode control */
-#define DDR_SDRAM_INTERVAL ((volatile uint32_t*)(DDR_BASE + 0x124)) /* DDR SDRAM interval configuration */
 #define DDR_SDRAM_CLK_CNTL ((volatile uint32_t*)(DDR_BASE + 0x130)) /* DDR SDRAM clock control */
 
 #define DDR_SDRAM_CFG_MEM_EN   0x80000000 /* SDRAM interface logic is enabled */
@@ -482,7 +481,6 @@ enum elbc_amask_sizes {
 #define ESPI_CSMODE_CSAFT(x) (((x) & 0xF) << 8)  /* CS assertion time in bits after frame end */
 #define ESPI_CSMODE_CSCG(x)  (((x) & 0xF) << 3)  /* Clock gaps between transmitted frames according to this size */
 
-
 #ifdef ENABLE_ELBC
 
 static volatile uint8_t* flash_buf;
@@ -492,33 +490,31 @@ static uint32_t          flash_idx;
 int ext_flash_read(uintptr_t address, uint8_t *data, int len);
 #endif
 
+/* generic share NXP QorIQ driver code */
+#include "nxp_ppc.c"
+
 
 /* local functions */
+#ifdef ENABLE_BUS_CLK_CALC
 static uint32_t hal_get_bus_clk(void)
 {
+    /* compute bus clock (system input 66MHz * ratio) */
     uint32_t bus_clk;
-#ifdef ENABLE_BUS_CLK_CALC
-    /* compute bus clock (system input 66MHz * ratio */
     uint32_t plat_ratio = get32(GUTS_PORPLLSR);
     /* mask and shift by 1 to get platform ratio */
     plat_ratio = ((plat_ratio & 0x3E) >> 1);
     bus_clk = SYS_CLK * plat_ratio;
     return bus_clk;
+}
 #else
-    return (uint32_t)(SYS_CLK * 6); /* can also be 8 */
+#define hal_get_bus_clk() (uint32_t)(SYS_CLK * 6)
 #endif
-}
 
-#if defined(ENABLE_ESPI) || defined(ENABLE_DDR)
-#ifdef BUILD_LOADER_STAGE1
-static
-#endif
-void udelay(unsigned long delay_us)
+#define DELAY_US (hal_get_bus_clk() / 1000000)
+static void udelay(uint32_t delay_us)
 {
-    delay_us *= (hal_get_bus_clk() / 1000000);
-    wait_ticks(delay_us);
+    wait_ticks(delay_us * DELAY_US);
 }
-#endif
 
 /* ---- eSPI Driver ---- */
 #ifdef ENABLE_ESPI
@@ -903,7 +899,7 @@ static int hal_flash_init(void)
     return ret;
 }
 
-void hal_ddr_init(void)
+static void hal_ddr_init(void)
 {
 #ifdef ENABLE_DDR
     uint32_t reg;
@@ -968,6 +964,12 @@ void hal_ddr_init(void)
 #endif /* ENABLE_DDR */
 }
 
+void hal_early_init(void)
+{
+    hal_ddr_init();
+}
+
+
 #ifdef ENABLE_PCIE
 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
 #define CONFIG_SYS_PCIE1_IO_PHYS  0xffc20000
@@ -987,18 +989,18 @@ static int hal_pcie_init(void)
     set_law(3, CONFIG_SYS_PCIE2_IO_PHYS,  LAW_TRGT_PCIE2, LAW_SIZE_64KB),
 
     /* Map TLB for PCIe */
-    set_tlb(1, 2, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+    set_tlb(1, 2, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, 0,
         MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256M, 1);
     set_tlb(1, 3, (CONFIG_SYS_PCIE2_MEM_VIRT + 0x10000000),
-                  (CONFIG_SYS_PCIE2_MEM_PHYS + 0x10000000),
+                  (CONFIG_SYS_PCIE2_MEM_PHYS + 0x10000000), 0,
         MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256M, 1);
-    set_tlb(1, 4, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+    set_tlb(1, 4, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 0,
         MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256M, 1);
     set_tlb(1, 5, (CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000),
-                  (CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000),
+                  (CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000), 0,
         MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256M, 1);
 
-    set_tlb(1, 6, CONFIG_SYS_PCIE2_IO_VIRT, CONFIG_SYS_PCIE2_IO_PHYS,
+    set_tlb(1, 6, CONFIG_SYS_PCIE2_IO_VIRT, CONFIG_SYS_PCIE2_IO_PHYS, 0,
         MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256K, 1);
     return 0;
 }
@@ -1011,7 +1013,7 @@ static int hal_cpld_init(void)
     /* Setup Local Access Window (LAW) for CPLD/BCSR */
     set_law(5, BCSR_BASE, LAW_TRGT_ELBC, LAW_SIZE_256KB);
     /* Setup TLB MMU (Translation Lookaside Buffer) for CPLD/BCSR */
-    set_tlb(1, 8, BCSR_BASE, BCSR_BASE, MAS3_SX | MAS3_SW | MAS3_SR,
+    set_tlb(1, 8, BCSR_BASE, BCSR_BASE, 0, MAS3_SX | MAS3_SW | MAS3_SR,
         MAS2_I | MAS2_G, 0, BOOKE_PAGESZ_256K, 1);
 
     /* setup eLBC for CPLD (CS1), 8-bit */
@@ -1504,7 +1506,7 @@ static void hal_mp_init(void)
 
     /* map reset page to bootpg so we can copy code there */
     disable_tlb1(i_tlb);
-    set_tlb(1, i_tlb, BOOT_ROM_ADDR, bootpg, /* tlb, epn, rpn */
+    set_tlb(1, i_tlb, BOOT_ROM_ADDR, bootpg, 0, /* tlb, epn, rpn */
         MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I, /* perms, wimge */
         0, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
 

hal/nxp_ppc.c

@@ -0,0 +1,23 @@
+/* nxp_ppc.c
+ *
+ * Copyright (C) 2023 wolfSSL Inc.
+ *
+ * This file is part of wolfBoot.
+ *
+ * wolfBoot is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfBoot is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
+ */
+
+/* This file gets directly included from nxp_ targets.
+ * This file contains shared driver code for all NXP QorIQ platforms */