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danielinuxdanielinux
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Fix cppcheck warnings
1 parent ad2caeb commit b5c8bc8

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13 files changed

+141
-139
lines changed

13 files changed

+141
-139
lines changed

‎hal/hifive1.c‎

Lines changed: 29 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -55,28 +55,28 @@
5555

5656
/* QSPI Fields */
5757
#define FESPI_IP_TXWM 0x1
58-
#define FESPI_RXDATA_FIFO_EMPTY (1 << 31)
59-
#define FESPI_TXDATA_FIFO_FULL (1 << 31)
60-
#define FESPI_FMT_DIR_TX (1 << 3)
58+
#define FESPI_RXDATA_FIFO_EMPTY (1UL << 31)
59+
#define FESPI_TXDATA_FIFO_FULL (1UL << 31)
60+
#define FESPI_FMT_DIR_TX (1UL << 3)
6161

6262
#define FESPI_CSMODE_AUTO 0x0UL
6363
#define FESPI_CSMODE_HOLD 0x2UL
6464
#define FESPI_CSMODE_MASK 0x3UL
6565

6666
#define FESPI_FCTRL_MODE_SEL 0x1UL
6767

68-
#define FESPI_FFMT_CMD_EN 0x1
69-
#define FESPI_FFMT_ADDR_LEN(x) (((x) & 0x7) << 1)
70-
#define FESPI_FFMT_PAD_CNT(x) (((x) & 0xf) << 4)
71-
#define FESPI_FFMT_CMD_PROTO(x) (((x) & 0x3) << 8)
72-
#define FESPI_FFMT_ADDR_PROTO(x) (((x) & 0x3) << 10)
73-
#define FESPI_FFMT_DATA_PROTO(x) (((x) & 0x3) << 12)
74-
#define FESPI_FFMT_CMD_CODE(x) (((x) & 0xff) << 16)
75-
#define FESPI_FFMT_PAD_CODE(x) (((x) & 0xff) << 24)
68+
#define FESPI_FFMT_CMD_EN 0x1UL
69+
#define FESPI_FFMT_ADDR_LEN(x) (((x) & 0x7) << 1UL)
70+
#define FESPI_FFMT_PAD_CNT(x) (((x) & 0xf) << 4UL)
71+
#define FESPI_FFMT_CMD_PROTO(x) (((x) & 0x3) << 8UL)
72+
#define FESPI_FFMT_ADDR_PROTO(x) (((x) & 0x3) << 10UL)
73+
#define FESPI_FFMT_DATA_PROTO(x) (((x) & 0x3) << 12UL)
74+
#define FESPI_FFMT_CMD_CODE(x) (((x) & 0xff) << 16UL)
75+
#define FESPI_FFMT_PAD_CODE(x) (((x) & 0xff) << 24UL)
7676

77-
#define FESPI_SCKDIV_MASK 0xFFF
77+
#define FESPI_SCKDIV_MASK 0xFFFUL
7878

79-
#define FESPI_TXMARK_MASK 0x3
79+
#define FESPI_TXMARK_MASK 0x3UL
8080

8181
/* FESPI_REG_FMT Fields */
8282
/* SPI I/O direction */
@@ -104,11 +104,11 @@
104104
#endif
105105

106106
/* SPI flash status fields (from FESPI_READ_STATUS command) */
107-
#define FESPI_RX_BSY (1 << 0)
108-
#define FESPI_RX_WE (1 << 1)
107+
#define FESPI_RX_BSY (1 << 0UL)
108+
#define FESPI_RX_WE (1 << 1UL)
109109

110110
/* QSPI Flash Sector Size */
111-
#define FESPI_FLASH_SECTOR_SIZE (4 * 1024)
111+
#define FESPI_FLASH_SECTOR_SIZE (4 * 1024UL)
112112

113113

114114
/* PRCI Registers */
@@ -135,8 +135,8 @@
135135

136136
#define HFROSCCFG_DIV 0x0000001FUL
137137
#define HFROSCCFG_TRIM 0x001F0000UL
138-
#define HFROSCCFG_EN (1UL << 30)
139-
#define HFROSCCFG_READY (1UL << 31)
138+
#define HFROSCCFG_EN (1UL << 30UL)
139+
#define HFROSCCFG_READY (1UL << 31UL)
140140
#define HFROSCCFG_DIV_SHIFT(d) ((d << 0) & HFROSCCFG_TRIM)
141141
#define HFROSCCFG_TRIM_SHIFT(t) ((t << 16) & HFROSCCFG_TRIM)
142142

@@ -154,19 +154,19 @@
154154
#define UART_REG_DIV (*(volatile uint32_t *)(UART0_BASE + 0x18))
155155

156156
/* TXDATA Fields */
157-
#define UART_TXEN (1 << 0)
158-
#define UART_TXFULL (1 << 31)
157+
#define UART_TXEN (1UL << 0)
158+
#define UART_TXFULL (1UL << 31)
159159

160160
/* RXDATA Fields */
161-
#define UART_RXEN (1 << 0)
162-
#define UART_RXEMPTY (1 << 31)
161+
#define UART_RXEN (1UL << 0)
162+
#define UART_RXEMPTY (1UL << 31)
163163

164164
/* TXCTRL Fields */
165-
#define UART_NSTOP (1 << 1)
166-
#define UART_TXCNT(count) ((0x7 & count) << 16)
165+
#define UART_NSTOP (1UL << 1)
166+
#define UART_TXCNT(count) ((0x7UL & count) << 16)
167167

168168
/* IP Fields */
169-
#define UART_TXWM (1 << 0)
169+
#define UART_TXWM (1UL << 0)
170170

171171

172172
/* Configuration Defaults */
@@ -183,16 +183,16 @@
183183
/* PLL Configuration */
184184
/* R and Q are fixed values for this PLL code */
185185
#define PLL_R (1) /* First Divisor: By 2 (takes 16Mhz PLLREF / 2 = 8MHz) */
186-
#define PLL_F(cpuHz) (((cpuHz / PLLREF_FREQ) * 2) - 1) /* Multiplier */
186+
#define PLL_F(cpuHz) (((cpuHz / PLLREF_FREQ) * 2U) - 1U) /* Multiplier */
187187
#define PLL_Q (1) /* Second Divisor: By 2 */
188188

189189
/* SPI Serial clock divisor */
190-
#define FESPI_SCKDIV_DEFAULT 0x03
191-
#define FESPI_SCKDIV_VAL(cpuHz, flashHz) (cpuHz / ((2 * flashHz) - 1))
190+
#define FESPI_SCKDIV_DEFAULT 0x03U
191+
#define FESPI_SCKDIV_VAL(cpuHz, flashHz) (cpuHz / ((2U * flashHz) - 1U))
192192

193193
/* UART baud initialize value */
194194
#ifndef UART_BAUD_INIT
195-
#define UART_BAUD_INIT 115200
195+
#define UART_BAUD_INIT 115200U
196196
#endif
197197

198198

‎hal/nxp_p1021.c‎

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -194,7 +194,7 @@ static int test_tpm(void);
194194
#define UART_LSR_THRE (0x20) /* Transmitter holding register empty */
195195

196196
/* P1021 eLBC (Enhanced Local Bus Controller) - RM 12.3 */
197-
#define ELBC_BASE (CCSRBAR + 0x5000)
197+
#define ELBC_BASE (CCSRBAR + 0x5000UL)
198198
#define ELBC_MAX_BANKS 8
199199
#define ELBC_BANK_SZ 8192
200200

@@ -216,51 +216,51 @@ static int test_tpm(void);
216216
#define ELBC_LTEATR ((volatile uint32_t*)(ELBC_BASE + 0xBC)) /* transfer error attributes register */
217217

218218

219-
#define ELBC_BR_ADDR(n) (((uint32_t)n) & 0xFFFF8000) /* Physical base address - upper 17-bits */
220-
#define ELBC_BR_PS(n) (((n) & 0x3) << 11) /* port size - 1=8-bit, 2=16-bit */
221-
#define ELBC_BR_DECC(n) (((n) & 0x3) << 9) /* data error checking - 0=disabled, 1=ECC check enable / gen disabled, 2=ECC check/gen enabled */
222-
#define ELBC_BR_WP (1 << 8) /* write protect */
223-
#define ELBC_BR_MSEL(n) (((n) & 0x7) << 5) /* machine select:
219+
#define ELBC_BR_ADDR(n) (((uint32_t)n) & 0xFFFF8000UL) /* Physical base address - upper 17-bits */
220+
#define ELBC_BR_PS(n) (((n) & 0x3UL) << 11) /* port size - 1=8-bit, 2=16-bit */
221+
#define ELBC_BR_DECC(n) (((n) & 0x3UL) << 9) /* data error checking - 0=disabled, 1=ECC check enable / gen disabled, 2=ECC check/gen enabled */
222+
#define ELBC_BR_WP (1UL << 8) /* write protect */
223+
#define ELBC_BR_MSEL(n) (((n) & 0x7UL) << 5) /* machine select:
224224
* 0=GPCM (General Purpose Chip-Select Machine)
225225
* 1=FCM (Flash Control Machine),
226226
* 4=UPMA, 5=UPMB, 6=UPMC (User Programmable Machines) */
227-
#define ELBC_BR_V (1 << 0) /* bank valid */
227+
#define ELBC_BR_V (1UL << 0) /* bank valid */
228228

229229
/* eLBC OR */
230230
#define ELBC_OR_AMASK(n) (((uint32_t)n) & 0xFFFF8000) /* Address mask - upper 17-bits */
231231

232232
/* eLBC OR (FCM) */
233-
#define ELBC_ORF_BCTLD (1 << 12) /* buffer control disable */
234-
#define ELBC_ORF_PGS (1 << 10) /* page size 0=512, 1=2048 bytes */
235-
#define ELBC_ORF_CSCT (1 << 9) /* chip select to command time - TRLX=0 (0=1, 1=4), TRLX=1 (0=2, 1=8) clock cycles */
236-
#define ELBC_ORF_CST (1 << 8) /* command setup time - TRLX=0 (0=0 or 1=0.25) TRLX=1 (0=0.5 or 1=1) clock cycles */
237-
#define ELBC_ORF_CHT (1 << 7) /* command hold time - TRLX=0 (0=0.5 or 1=1) TRLX=1 (0=1.5 or 1=2) clock cycles */
238-
#define ELBC_ORF_SCY(n) (((n) & 0x7) << 4) /* cycle length in bus clocks (0-7 bus clock cycle wait states) */
239-
#define ELBC_ORF_RST (1 << 3) /* read time setup - read enable asserted 1 clock */
240-
#define ELBC_ORF_TRLX (1 << 2) /* timing related */
241-
#define ELBC_ORF_EHTR (1 << 1) /* extended hold time - LRLX=0 (0=1 or 1=2), LRLX=1 (0=2 or 1=8) inserted idle clock cycles */
233+
#define ELBC_ORF_BCTLD (1UL << 12) /* buffer control disable */
234+
#define ELBC_ORF_PGS (1UL << 10) /* page size 0=512, 1=2048 bytes */
235+
#define ELBC_ORF_CSCT (1UL << 9) /* chip select to command time - TRLX=0 (0=1, 1=4), TRLX=1 (0=2, 1=8) clock cycles */
236+
#define ELBC_ORF_CST (1UL << 8) /* command setup time - TRLX=0 (0=0 or 1=0.25) TRLX=1 (0=0.5 or 1=1) clock cycles */
237+
#define ELBC_ORF_CHT (1UL << 7) /* command hold time - TRLX=0 (0=0.5 or 1=1) TRLX=1 (0=1.5 or 1=2) clock cycles */
238+
#define ELBC_ORF_SCY(n) (((n) & 0x7UL) << 4) /* cycle length in bus clocks (0-7 bus clock cycle wait states) */
239+
#define ELBC_ORF_RST (1UL << 3) /* read time setup - read enable asserted 1 clock */
240+
#define ELBC_ORF_TRLX (1UL << 2) /* timing related */
241+
#define ELBC_ORF_EHTR (1UL << 1) /* extended hold time - LRLX=0 (0=1 or 1=2), LRLX=1 (0=2 or 1=8) inserted idle clock cycles */
242242

243243
/* eLBC OR (GPCM) */
244-
#define ELBC_ORG_CSCT (1 << 11)
245-
#define ELBC_ORG_XACS (1 << 8)
246-
#define ELBC_ORG_SCY (1 << 4)
247-
#define ELBC_ORG_TRLX (1 << 2)
248-
#define ELBC_ORG_EHTR (1 << 1)
249-
#define ELBC_ORG_EAD (1 << 0)
244+
#define ELBC_ORG_CSCT (1UL << 11)
245+
#define ELBC_ORG_XACS (1UL << 8)
246+
#define ELBC_ORG_SCY (1UL << 4)
247+
#define ELBC_ORG_TRLX (1UL << 2)
248+
#define ELBC_ORG_EHTR (1UL << 1)
249+
#define ELBC_ORG_EAD (1UL << 0)
250250

251251

252-
#define ELBC_LSOR_BANK(n) ((n) & (ELBC_MAX_BANKS-1)) /* flash bank 0-7 */
252+
#define ELBC_LSOR_BANK(n) ((n) & (ELBC_MAX_BANKS-1UL)) /* flash bank 0-7 */
253253

254254
#define ELBC_LBCR_ABSWP (1 << 19) /* Address byte swap for 16-bit port size */
255255
#define ELBC_LBCR_BMTPS(n) ((n) & 0xF) /* Bus monitor timer prescale */
256256

257257
#define ELBC_FMR_CWTO(n) (((n) & 0xF) << 12) /* command wait timeout 0=256 cycles, 15=8,388,608 cycles of LCLK */
258258
#define ELBC_FMR_BOOT (1 << 11) /* flash auto-boot lead mode 0=FCM is op normal, 1=eLBC autoload 4-Kbyte boot block */
259259
#define ELBC_FMR_ECCM (1 << 8) /* ECC mode 0=ECC is checked/calc 6/8 spare, 1=8/10 spare */
260-
#define ELBC_FMR_AL(n) (((n) & 0x3) << 4) /* address length 0=2 bytes, 1=3 bytes, 2=4 bytes issued for page address */
261-
#define ELBC_FMR_OP(n) (((n) & 0x3) << 0) /* flash operation 0=normal, 1=sim auto-boot block load, 2=exe FIR cmd w/write protect enable, 3=exe FIR cmd */
260+
#define ELBC_FMR_AL(n) (((n) & 0x3UL) << 4) /* address length 0=2 bytes, 1=3 bytes, 2=4 bytes issued for page address */
261+
#define ELBC_FMR_OP(n) (((n) & 0x3UL) << 0) /* flash operation 0=normal, 1=sim auto-boot block load, 2=exe FIR cmd w/write protect enable, 3=exe FIR cmd */
262262

263-
#define ELBC_FIR_OP(s,op) ((op) & 0xF) << (28 - ((s % 8) * 4)) /* up to 8 sequences of instructions */
263+
#define ELBC_FIR_OP(s,op) ((op) & 0xFUL) << (28 - ((s % 8) * 4)) /* up to 8 sequences of instructions */
264264
#define ELBC_FIR_OP_NOP 0 /* No-operation and end of operation sequence */
265265
#define ELBC_FIR_OP_CA 1 /* Issue current column address as set in FPAR, with length set by ORx[PGS] */
266266
#define ELBC_FIR_OP_PA 2 /* Issue current block+page address as set in FBAR and FPAR, with length set by FMR[AL] */
@@ -277,7 +277,7 @@ static int test_tpm(void);
277277
#define ELBC_FIR_OP_CW1 13 /* Wait for LFRB to return high or time-out, then issue command from FCR[CMD1] */
278278
#define ELBC_FIR_OP_RBW 14 /* Wait for LFRB to return high or time-out, then read FBCR bytes of data from Flash device into current FCM RAM buffer */
279279
#define ELBC_FIR_OP_RSW 15 /* Wait for LFRB to return high or time-out, then read one byte (8b port) of data from Flash device into next AS field of MDR */
280-
#define ELBC_FCR_CMD(s,cmd) (((cmd) & 0xFF) << (24 - ((s % 4) * 8))) /* up to 4 command opcodes */
280+
#define ELBC_FCR_CMD(s,cmd) (((cmd) & 0xFFUL) << (24 - ((s % 4) * 8))) /* up to 4 command opcodes */
281281

282282
#define ELBC_LCRR_CLKDIV_MASK 0x0000001F
283283
#define ELBC_LCRR_CLKDIV_4 0x2

‎hal/nxp_ppc.h‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -28,22 +28,22 @@
2828
#define CORE_E500
2929
#define LAW_MAX_ENTRIES 12
3030

31-
#define CCSRBAR_DEF (0xFF700000) /* P1021RM 4.3 default base */
31+
#define CCSRBAR_DEF (0xFF700000UL) /* P1021RM 4.3 default base */
3232
#define CCSRBAR_SIZE BOOKE_PAGESZ_1M
3333

3434
#define ENABLE_DDR
35-
#define DDR_SIZE (512 * 1024 * 1024)
35+
#define DDR_SIZE (512UL * 1024UL * 1024UL)
3636

3737
/* Memory used for transferring blocks to/from NAND.
3838
* Maps to eLBC FCM internal 8KB region (by hardware) */
39-
#define FLASH_BASE_ADDR 0xFC000000
39+
#define FLASH_BASE_ADDR 0xFC000000UL
4040

4141
#ifdef BUILD_LOADER_STAGE1
4242
/* First stage loader features */
4343

4444
#define ENABLE_L2_CACHE
45-
#define L2SRAM_ADDR (0xF8F80000) /* L2 as SRAM */
46-
#define L2SRAM_SIZE (256 * 1024)
45+
#define L2SRAM_ADDR (0xF8F80000UL) /* L2 as SRAM */
46+
#define L2SRAM_SIZE (256UL * 1024UL)
4747

4848
#define INITIAL_SRAM_ADDR L2SRAM_ADDR
4949
#define INITIAL_SRAM_LAW_SZ LAW_SIZE_256KB
@@ -55,7 +55,7 @@
5555
#define ENABLE_L2_CACHE
5656

5757
/* Relocate CCSRBAR */
58-
#define CCSRBAR 0xFFE00000
58+
#define CCSRBAR 0xFFE00000UL
5959

6060
#define ENABLE_INTERRUPTS
6161
#endif
@@ -88,7 +88,7 @@
8888
#define ENABLE_DDR
8989
#define DDR_SIZE (2048ULL * 1024ULL * 1024ULL)
9090

91-
#define FLASH_BASE_ADDR 0xEC000000
91+
#define FLASH_BASE_ADDR 0xEC000000UL
9292
#define FLASH_BASE_PHYS_HIGH 0xFULL
9393
#define FLASH_LAW_SIZE LAW_SIZE_64MB
9494
#define FLASH_TLB_PAGESZ BOOKE_PAGESZ_64M
@@ -101,7 +101,7 @@
101101
#define CORE_E6500
102102
#define LAW_MAX_ENTRIES 32
103103

104-
#define CCSRBAR_DEF (0xFE000000) /* T2080RM 4.3.1 default base */
104+
#define CCSRBAR_DEF (0xFE000000UL) /* T2080RM 4.3.1 default base */
105105
#define CCSRBAR_SIZE BOOKE_PAGESZ_16M
106106

107107
/* relocate to 64-bit 0xE_ */
@@ -111,8 +111,8 @@
111111
#define ENABLE_L1_CACHE
112112
#define ENABLE_L2_CACHE
113113

114-
#define L2SRAM_ADDR (0xF8F80000) /* L2 as SRAM */
115-
#define L2SRAM_SIZE (256 * 1024)
114+
#define L2SRAM_ADDR (0xF8F80000UL) /* L2 as SRAM */
115+
#define L2SRAM_SIZE (256UL * 1024UL)
116116

117117
#define INITIAL_SRAM_ADDR L2SRAM_ADDR
118118
#define INITIAL_SRAM_LAW_SZ LAW_SIZE_256KB
@@ -122,9 +122,9 @@
122122
#define ENABLE_INTERRUPTS
123123

124124
#define ENABLE_DDR
125-
#define DDR_SIZE (8192 * 1024 * 1024)
125+
#define DDR_SIZE (8192UL * 1024UL * 1024UL)
126126

127-
#define FLASH_BASE_ADDR 0xE8000000
127+
#define FLASH_BASE_ADDR 0xE8000000UL
128128
#define FLASH_BASE_PHYS_HIGH 0x0ULL
129129
#define FLASH_LAW_SIZE LAW_SIZE_128MB
130130
#define FLASH_TLB_PAGESZ BOOKE_PAGESZ_128M
@@ -138,18 +138,18 @@
138138

139139
/* boot address */
140140
#ifndef BOOT_ROM_ADDR
141-
#define BOOT_ROM_ADDR 0xFFFFF000
141+
#define BOOT_ROM_ADDR 0xFFFFF000UL
142142
#endif
143143
#ifndef BOOT_ROM_SIZE
144-
#define BOOT_ROM_SIZE (4*1024)
144+
#define BOOT_ROM_SIZE (4UL*1024UL)
145145
#endif
146146

147147
/* reset vector */
148148
#define RESET_VECTOR (BOOT_ROM_ADDR + (BOOT_ROM_SIZE - 4))
149149

150150
/* CCSRBAR */
151151
#ifndef CCSRBAR_DEF
152-
#define CCSRBAR_DEF 0xFE000000
152+
#define CCSRBAR_DEF 0xFE000000UL
153153
#endif
154154
#ifndef CCSRBAR
155155
#define CCSRBAR CCSRBAR_DEF
@@ -163,7 +163,7 @@
163163

164164
/* DDR */
165165
#ifndef DDR_ADDRESS
166-
#define DDR_ADDRESS 0x00000000
166+
#define DDR_ADDRESS 0x00000000UL
167167
#endif
168168

169169
/* L1 */

‎hal/skeleton.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,7 @@ void hal_prepare_boot(void)
4040

4141
int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
4242
{
43+
return 0; /* on success. */
4344
}
4445

4546
void RAMFUNCTION hal_flash_unlock(void)
@@ -52,5 +53,6 @@ void RAMFUNCTION hal_flash_lock(void)
5253

5354
int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
5455
{
56+
return 0; /* on success. */
5557
}
5658

‎hal/stm32f4.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -84,7 +84,7 @@
8484
#define FLASH_SR_OPERR (1 << 1)
8585
#define FLASH_SR_EOP (1 << 0)
8686

87-
#define FLASH_CR_LOCK (uint32_t)(1 << 31)
87+
#define FLASH_CR_LOCK (1UL << 31)
8888
#define FLASH_CR_ERRIE (1 << 25)
8989
#define FLASH_CR_EOPIE (1 << 24)
9090
#define FLASH_CR_STRT (1 << 16)

‎hal/stm32f7.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,7 @@
8686
#define FLASH_SR_OPERR (1 << 1)
8787
#define FLASH_SR_EOP (1 << 0)
8888

89-
#define FLASH_CR_LOCK (1 << 31)
89+
#define FLASH_CR_LOCK (1UL << 31)
9090
#define FLASH_CR_ERRIE (1 << 25)
9191
#define FLASH_CR_EOPIE (1 << 24)
9292
#define FLASH_CR_STRT (1 << 16)

‎hal/stm32g0.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -80,7 +80,7 @@
8080
#define FLASH_SR_PROGERR (1 << 3)
8181
#define FLASH_SR_EOP (1 << 0) /* RM0444 - 3.7.4 - FLASH_SR */
8282

83-
#define FLASH_CR_LOCK (1 << 31) /* RM0444 - 3.7.5 - FLASH_CR */
83+
#define FLASH_CR_LOCK (1UL << 31) /* RM0444 - 3.7.5 - FLASH_CR */
8484
#define FLASH_CR_STRT (1 << 16) /* RM0444 - 3.7.5 - FLASH_CR */
8585

8686
#define FLASH_CR_PER (1 << 1) /* RM0444 - 3.7.5 - FLASH_CR */

‎hal/stm32l5_ns.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -165,7 +165,7 @@
165165
#define FLASH_CR_ERRIE (1 << 25)
166166
#define FLASH_CR_OBL_LAUNCH (1 << 27)
167167
#define FLASH_CR_OPTLOCK (1 << 30)
168-
#define FLASH_CR_LOCK (1 << 31)
168+
#define FLASH_CR_LOCK (1UL << 31)
169169

170170
#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00))
171171
#define FLASH_ACR_LATENCY_MASK (0x0F)

‎hal/stm32u5.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -177,7 +177,7 @@ int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
177177
{
178178
uint32_t end_address;
179179
uint32_t p;
180-
volatile uint32_t *cr;
180+
volatile uint32_t *cr = &FLASH_NS_CR;
181181

182182
flash_clear_errors(0);
183183
if (len == 0)

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