Allow build-time adjustment of QSPI reference clock and divisor. Eliminate ZCU102 macro (not needed). Add QSPI init message with ref clock, divisor, bus and IO mode (Poll or DMA).

Author: dgarske

config/examples/zynqmp.config

@@ -3,9 +3,6 @@ TARGET?=zynq
 
 WOLFBOOT_VERSION?=0
 
-# Default to ZCU102 as hardware platform (QSPI sizes)
-CFLAGS_EXTRA+=-DZCU102
-
 # RSA 4096-bit with SHA3-384
 SIGN?=RSA4096
 HASH?=SHA3
@@ -80,7 +77,10 @@ CROSS_COMPILE=aarch64-none-elf-
 # Speed up reads from flash by using larger blocks
 CFLAGS_EXTRA+=-DWOLFBOOT_SHA_BLOCK_SIZE=4096
 
-# QSPI Clock at 0=150MHz, 1=75MHz, 2=37.5MHz (default)
+# QSPI Reference Clock: Ref (125MHz default)
+#CFLAGS_EXTRA+=-DGQSPI_CLK_REF=300000000
+
+# QSPI Bus Divisor: (2 << div) = BUS (0=div2, 1=div4, 2=div8)
 #CFLAGS_EXTRA+=-DGQSPI_CLK_DIV=0
 
 # QSPI force IO mode (default is faster DMA mode)

hal/zynq.c

@@ -44,7 +44,7 @@
     /* Xilinx BSP Driver */
     #include "xqspipsu.h"
     #ifndef QSPI_DEVICE_ID
-    #define QSPI_DEVICE_ID		XPAR_XQSPIPSU_0_DEVICE_ID
+    #define QSPI_DEVICE_ID      XPAR_XQSPIPSU_0_DEVICE_ID
     #endif
     #ifndef QSPI_CLK_PRESACALE
     #define QSPI_CLK_PRESACALE  XQSPIPSU_CLK_PRESCALE_8
@@ -104,7 +104,7 @@ void uart_init(void)
     ZYNQMP_UART_RXTOUT = 0;
 
     /* baud (115200) = master clk / (BR_GEN * (BR_DIV + 1)) */
-    ZYNQMP_UART_BR_GEN = UART_MASTER_CLOCK / (DEBUG_UART_BAUD * (DEBUG_UART_DIV+1));
+    ZYNQMP_UART_BR_GEN = UART_CLK_REF / (DEBUG_UART_BAUD * (DEBUG_UART_DIV+1));
     ZYNQMP_UART_BR_DIV = DEBUG_UART_DIV;
 
     /* Reset TX/RX */
@@ -843,6 +843,16 @@ void qspi_init(uint32_t cpu_clock, uint32_t flash_freq)
     }
 #else
     /* QSPI bare-metal driver */
+    wolfBoot_printf("QSPI Init: Ref=%dMHz, Div=%d, Bus=%d, IO=%s\n",
+        GQSPI_CLK_REF/1000000,
+        (2 << GQSPI_CLK_DIV),
+        (GQSPI_CLK_REF / (2 << GQSPI_CLK_DIV)),
+    #ifdef GQSPI_MODE_IO
+        "Poll"
+    #else
+        "DMA"
+    #endif
+    );
 
     /* Disable Linear Mode in case FSBL enabled it */
     LQSPI_EN = 0;
@@ -872,21 +882,20 @@ void qspi_init(uint32_t cpu_clock, uint32_t flash_freq)
     reg_cfg &= ~(GQSPI_CFG_CLK_POL | GQSPI_CFG_CLK_PH); /* Use POL=0,PH=0 */
     GQSPI_CFG = reg_cfg;
 
-#if GQSPI_CLK_DIV >= 1 /* 125/4=31.25MHz */
+#if (GQSPI_CLK_REF / (2 << GQSPI_CLK_DIV)) <= 40000000 /* 40MHz */
     /* At <40 MHz, the Quad-SPI controller should be in non-loopback mode with
      * the clock and data tap delays bypassed. */
     IOU_TAPDLY_BYPASS |= IOU_TAPDLY_BYPASS_LQSPI_RX;
     GQSPI_LPBK_DLY_ADJ = 0;
     GQSPI_DATA_DLY_ADJ = 0;
-#elif GQSPI_CLK_DIV >= 0 /* 125/2 = 62.5MHz */
+#elif (GQSPI_CLK_REF / (2 << GQSPI_CLK_DIV)) <= 100000000 /* 100MHz */
     /* At <100 MHz, the Quad-SPI controller should be in clock loopback mode
      * with the clock tap delay bypassed, but the data tap delay enabled. */
     IOU_TAPDLY_BYPASS |= IOU_TAPDLY_BYPASS_LQSPI_RX;
     GQSPI_LPBK_DLY_ADJ = GQSPI_LPBK_DLY_ADJ_USE_LPBK;
     GQSPI_DATA_DLY_ADJ = (GQSPI_DATA_DLY_ADJ_USE_DATA_DLY |
                           GQSPI_DATA_DLY_ADJ_DATA_DLY_ADJ(2));
-#endif
-#if 0
+#elif (GQSPI_CLK_REF / (2 << GQSPI_CLK_DIV)) <= 150000000 /* 150MHz */
     /* At <150 MHz, only the generic controller can be used.
      * The generic controller should be in clock loopback mode and the clock
      * tap delay enabled, but the data tap delay disabled. */

hal/zynq.h

@@ -51,15 +51,10 @@
 #define XPAR_PSU_DDR_1_S_AXI_BASEADDR 0x800000000
 #define XPAR_PSU_DDR_1_S_AXI_HIGHADDR 0x87FFFFFFF
 
-/* Clocking */
-#define CORTEXA53_0_CPU_CLK_FREQ_HZ    1199880127
-#define CORTEXA53_0_TIMESTAMP_CLK_FREQ 99990005
-#define UART_MASTER_CLOCK              99990005
-#define GQSPI_CLK_FREQ_HZ              124987511
-
 /* IOP System-level Control */
 #define IOU_SLCR_BASSE             0xFF180000
-#define IOU_TAPDLY_BYPASS          (*((volatile uint32_t*)(IOU_SLCR_BASSE + 0x390)))
+#define IOU_TAPDLY_BYPASS_ADDR     (IOU_SLCR_BASSE + 0x390)
+#define IOU_TAPDLY_BYPASS          (*((volatile uint32_t*)IOU_TAPDLY_BYPASS_ADDR))
 #define IOU_TAPDLY_BYPASS_LQSPI_RX (1UL << 2) /* LQSPI Tap Delay Enable on Rx Clock signal. 0: enable. 1: disable (bypass tap delay). */
 
 /* QSPI bare-metal driver */
@@ -186,8 +181,12 @@
 #define GQSPIDMA_ISR_ALL_MASK  0xFEU
 
 /* QSPI Configuration (bare-metal only) */
+
+#ifndef GQSPI_CLK_REF
+#define GQSPI_CLK_REF          125000000 /* QSPI Reference Clock */
+#endif
 #ifndef GQSPI_CLK_DIV
-#define GQSPI_CLK_DIV          2 /* (CLK (300MHz) / (2 << DIV) = BUS): 0=DIV2, 1=DIV4, 2=DIV8 */
+#define GQSPI_CLK_DIV          2 /* (QSPI_REF_CLK (125MHZ) / (2 << DIV) = BUS): 0=DIV2, 1=DIV4, 2=DIV8 */
 #endif
 #define GQSPI_CS_ASSERT_CLOCKS 5 /* CS Setup Time (tCSS) - num of clock cycles foes in IMM */
 #define GQSPI_FIFO_WORD_SZ     4
@@ -221,29 +220,20 @@
 
 
 /* Flash Parameters:
- * Micron Serial NOR Flash Memory 64KB Sector Erase MT25QU512ABB
- * Stacked device (two 512Mb (64MB))
- * Dual Parallel so total addressable size is double
+ * Micron Serial NOR Flash Memory 4K Sector Erase MT25QU512ABB
+ * ZCU102 uses dual Parallel (stacked device 2*64MB)
+ * MT25QU512 - Read FlashID: 20 BB 20 (64MB)
+ * MT25QU01G - Read FlashID: 20 BB 21 (128MB)
+ * MT25QU02G - Read FlashID: 20 BB 22 (256MB)
  */
-#ifndef FLASH_DEVICE_SIZE
-    #ifdef ZCU102
-        /* 64*2 (dual parallel) = 128MB */
-        #define FLASH_DEVICE_SIZE (2 *  64 * 1024 * 1024) /* MT25QU512ABB */
-    #else
-        /* 128*2 (dual parallel) = 256MB */
-        #define FLASH_DEVICE_SIZE (2 * 128 * 1024 * 1024) /* MT25QU01GBBB */
-    #endif
-#endif
 #ifndef FLASH_PAGE_SIZE
-    #ifdef ZCU102
-        /* MT25QU512ABB - Read FlashID: 20 BB 20 */
-        #define FLASH_PAGE_SIZE 256
-    #else
-        /* MT25QU01GBBB - Read FlashID: 20 BB 21 */
+    #if defined(GQPI_USE_DUAL_PARALLEL) && GQPI_USE_DUAL_PARALLEL == 1
+        /* each flash page size is 256 bytes, for dual parallel double it */
         #define FLASH_PAGE_SIZE 512
+    #else
+        #define FLASH_PAGE_SIZE 256
     #endif
 #endif
-#define FLASH_NUM_SECTORS      (FLASH_DEVICE_SIZE/WOLFBOOT_SECTOR_SIZE)
 
 
 /* Flash Commands */
@@ -370,6 +360,10 @@
     #define DEBUG_UART_BASE     ZYNQMP_UART0_BASE
 #endif
 
+#ifndef UART_CLK_REF
+    #define UART_CLK_REF        100000000
+#endif
+
 #ifndef DEBUG_UART_BAUD
     #define DEBUG_UART_BAUD     115200
     #define DEBUG_UART_DIV      6