Various STM32 TrustZone improvements

mattia-moffa · mattia-moffa · commit c1887cd636f8 · 2025-11-19T16:50:50.000+01:00
- New config flags for flash geometry
- New script to automatically set option bytes
- End of stack address fix for the STM32U5 test app
- STM32U5 support for NUCLEO-U575ZI-Q (previously only supported
  discovery board)
diff --git a/Makefile b/Makefile
@@ -402,6 +402,10 @@ $(LSCRIPT): $(LSCRIPT_IN) FORCE
 		sed -e "s/@ARCH_FLASH_OFFSET@/$(ARCH_FLASH_OFFSET)/g" | \
 		sed -e "s/@BOOTLOADER_PARTITION_SIZE@/$(BOOTLOADER_PARTITION_SIZE)/g" | \
 		sed -e "s/@WOLFBOOT_ORIGIN@/$(WOLFBOOT_ORIGIN)/g" | \
+		sed -e "s/@WOLFBOOT_KEYVAULT_ADDRESS@/$(WOLFBOOT_KEYVAULT_ADDRESS)/g" | \
+		sed -e "s/@WOLFBOOT_KEYVAULT_SIZE@/$(WOLFBOOT_KEYVAULT_SIZE)/g" | \
+		sed -e "s/@WOLFBOOT_NSC_ADDRESS@/$(WOLFBOOT_NSC_ADDRESS)/g" | \
+		sed -e "s/@WOLFBOOT_NSC_SIZE@/$(WOLFBOOT_NSC_SIZE)/g" | \
 		sed -e "s/@WOLFBOOT_PARTITION_BOOT_ADDRESS@/$(WOLFBOOT_PARTITION_BOOT_ADDRESS)/g" | \
 		sed -e "s/@WOLFBOOT_PARTITION_SIZE@/$(WOLFBOOT_PARTITION_SIZE)/g" | \
 		sed -e "s/@WOLFBOOT_PARTITION_UPDATE_ADDRESS@/$(WOLFBOOT_PARTITION_UPDATE_ADDRESS)/g" | \
@@ -480,6 +484,8 @@ include/target.h: $(TARGET_H_TEMPLATE) FORCE
 	$(Q)cat $(TARGET_H_TEMPLATE) | \
 	sed -e "s/@WOLFBOOT_PARTITION_SIZE@/$(WOLFBOOT_PARTITION_SIZE)/g" | \
 	sed -e "s/@WOLFBOOT_SECTOR_SIZE@/$(WOLFBOOT_SECTOR_SIZE)/g" | \
+	sed -e "s/@WOLFBOOT_NSC_ADDRESS@/$(WOLFBOOT_NSC_ADDRESS)/g" | \
+	sed -e "s/@WOLFBOOT_NSC_SIZE@/$(WOLFBOOT_NSC_SIZE)/g" | \
 	sed -e "s/@WOLFBOOT_PARTITION_BOOT_ADDRESS@/$(WOLFBOOT_PARTITION_BOOT_ADDRESS)/g" | \
 	sed -e "s/@WOLFBOOT_PARTITION_UPDATE_ADDRESS@/$(WOLFBOOT_PARTITION_UPDATE_ADDRESS)/g" | \
 	sed -e "s/@WOLFBOOT_PARTITION_SWAP_ADDRESS@/$(WOLFBOOT_PARTITION_SWAP_ADDRESS)/g" | \
diff --git a/config/examples/stm32h5-tz-dualbank-otp-lms.config b/config/examples/stm32h5-tz-dualbank-otp-lms.config
@@ -20,6 +20,10 @@ RAM_CODE?=1
 DUALBANK_SWAP?=1
 WOLFBOOT_PARTITION_SIZE?=0xA0000
 WOLFBOOT_SECTOR_SIZE?=0x2000
+WOLFBOOT_KEYVAULT_ADDRESS?=0x0C040000
+WOLFBOOT_KEYVAULT_SIZE?=0x1C000
+WOLFBOOT_NSC_ADDRESS?=0x0C05C000
+WOLFBOOT_NSC_SIZE?=0x4000
 WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08060000
 WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x0C160000
 WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xFFFFFFFF
diff --git a/config/examples/stm32h5-tz-dualbank-otp.config b/config/examples/stm32h5-tz-dualbank-otp.config
@@ -20,6 +20,10 @@ RAM_CODE?=1
 DUALBANK_SWAP?=1
 WOLFBOOT_PARTITION_SIZE?=0xA0000
 WOLFBOOT_SECTOR_SIZE?=0x2000
+WOLFBOOT_KEYVAULT_ADDRESS?=0x0C040000
+WOLFBOOT_KEYVAULT_SIZE?=0x1C000
+WOLFBOOT_NSC_ADDRESS?=0x0C05C000
+WOLFBOOT_NSC_SIZE?=0x4000
 WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08060000
 WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x0C160000
 WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xFFFFFFFF
diff --git a/config/examples/stm32h5-tz-dualbank.config b/config/examples/stm32h5-tz-dualbank.config
@@ -20,6 +20,10 @@ RAM_CODE?=1
 DUALBANK_SWAP?=1
 WOLFBOOT_PARTITION_SIZE?=0xA0000
 WOLFBOOT_SECTOR_SIZE?=0x2000
+WOLFBOOT_KEYVAULT_ADDRESS?=0x0C040000
+WOLFBOOT_KEYVAULT_SIZE?=0x1C000
+WOLFBOOT_NSC_ADDRESS?=0x0C05C000
+WOLFBOOT_NSC_SIZE?=0x4000
 WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08060000
 WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x0C160000
 WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xFFFFFFFF
diff --git a/config/examples/stm32h5-tz.config b/config/examples/stm32h5-tz.config
@@ -20,6 +20,10 @@ RAM_CODE?=1
 DUALBANK_SWAP?=0
 WOLFBOOT_PARTITION_SIZE?=0xA0000
 WOLFBOOT_SECTOR_SIZE?=0x2000
+WOLFBOOT_KEYVAULT_ADDRESS?=0x0C040000
+WOLFBOOT_KEYVAULT_SIZE?=0x1C000
+WOLFBOOT_NSC_ADDRESS?=0x0C05C000
+WOLFBOOT_NSC_SIZE?=0x4000
 WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08060000
 WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x0C100000
 WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x0C1A0000
diff --git a/config/examples/stm32l5-wolfcrypt-tz.config b/config/examples/stm32l5-wolfcrypt-tz.config
@@ -20,6 +20,10 @@ RAM_CODE?=0
 DUALBANK_SWAP?=0
 WOLFBOOT_PARTITION_SIZE?=0x1F800
 WOLFBOOT_SECTOR_SIZE?=0x800
+WOLFBOOT_KEYVAULT_ADDRESS?=0x0C020000
+WOLFBOOT_KEYVAULT_SIZE?=0x18000
+WOLFBOOT_NSC_ADDRESS?=0xC038000
+WOLFBOOT_NSC_SIZE?=0x8000
 WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08040000
 WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x805F800
 WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x0807F000
diff --git a/config/examples/stm32u5-wolfcrypt-tz.config b/config/examples/stm32u5-wolfcrypt-tz.config
@@ -20,6 +20,10 @@ RAM_CODE?=0
 DUALBANK_SWAP?=0
 WOLFBOOT_PARTITION_SIZE?=0x1F800
 WOLFBOOT_SECTOR_SIZE?=0x800
+WOLFBOOT_KEYVAULT_ADDRESS?=0x0C020000
+WOLFBOOT_KEYVAULT_SIZE?=0x18000
+WOLFBOOT_NSC_ADDRESS?=0x0C038000
+WOLFBOOT_NSC_SIZE?=0x8000
 WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08040000
 WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x805F800
 WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x0807F000
diff --git a/config/examples/stm32u5.config b/config/examples/stm32u5.config
@@ -22,6 +22,10 @@ RAM_CODE?=0
 DUALBANK_SWAP?=0
 WOLFBOOT_PARTITION_SIZE?=0x1F800
 WOLFBOOT_SECTOR_SIZE?=0x800
+WOLFBOOT_KEYVAULT_ADDRESS?=0x0C020000
+WOLFBOOT_KEYVAULT_SIZE?=0x18000
+WOLFBOOT_NSC_ADDRESS?=0x0C038000
+WOLFBOOT_NSC_SIZE?=0x8000
 WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08040000
 WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x805F800
 WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x0807F000
diff --git a/docs/STM32-TZ.md b/docs/STM32-TZ.md
@@ -55,6 +55,17 @@ image header size must be supplied as an environment variable. For example:
 IMAGE_HEADER_SIZE=1024 ./tools/keytools/sign --sha256 --ecc256 myapp.bin wolfboot_signing_private_key.der 1
 ```
 
+### Setting option bytes automatically
+
+In order to use wolfBoot with an STM32 device, the device's option bytes need
+to be consistent with wolfBoot's configuration. The script at
+[tools/scripts/set-stm32-tz-option-bytes.sh](tools/scripts/set-stm32-tz-option-bytes.sh)
+will attempt to read the wolfBoot `.config` file and automatically calculate
+and set your device's TrustZone-related option bytes according to it, using
+`STM32_Programmer_CLI`, which is part of the
+[STM32CubeProg](https://www.st.com/en/development-tools/stm32cubeprog.html)
+tool.
+
 ### NSC API
 
 wolfBoot provides a few Non-Secure Callable functions to allow a non-secure
diff --git a/hal/stm32_tz.c b/hal/stm32_tz.c
@@ -37,6 +37,7 @@
 
 #include "image.h"
 #include "hal.h"
+#include "target.h"
 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) && (!defined(FLAGS_HOME) || !defined(DISABLE_BACKUP))
 
 
@@ -297,7 +298,8 @@ void hal_tz_sau_init(void)
     /* SAU is set up before staging. Set up all areas as secure. */
 
     /* Non-secure callable: NSC functions area */
-    sau_init_region(0, 0x0C040000, 0x0C05FFFF, 1);
+    sau_init_region(0, WOLFBOOT_NSC_ADDRESS,
+            WOLFBOOT_NSC_ADDRESS + WOLFBOOT_NSC_SIZE - 1, 1);
 
     /* Secure: application flash area (first bank) */
     sau_init_region(1, WOLFBOOT_PARTITION_BOOT_ADDRESS, FLASH_BANK2_BASE - 1, 0);
@@ -331,10 +333,11 @@ void hal_tz_sau_init(void)
 void hal_tz_sau_init(void)
 {
     /* Non-secure callable: NSC functions area */
-    sau_init_region(0, 0x0C038000, 0x0C040000, 1);
+    sau_init_region(0, WOLFBOOT_NSC_ADDRESS,
+            WOLFBOOT_NSC_ADDRESS + WOLFBOOT_NSC_SIZE - 1, 1);
 
     /* Non-secure: application flash area */
-    sau_init_region(1, 0x08040000, 0x0807FFFF, 0);
+    sau_init_region(1, WOLFBOOT_PARTITION_BOOT_ADDRESS, WOLFBOOT_PARTITION_BOOT_ADDRESS + 2 * WOLFBOOT_PARTITION_SIZE - 1, 0);
 
     /* Non-secure RAM region in SRAM1/SRAM2 */
     sau_init_region(2, 0x20020000, 0x2003FFFF, 0);
diff --git a/hal/stm32h5.ld b/hal/stm32h5.ld
@@ -1,12 +1,11 @@
 MEMORY
 {
-    /* If FLASH_KEYVAULT or FLASH_NSC length is adjusted FLASH length needs adjusted too */
-    FLASH (rx) :    ORIGIN = @WOLFBOOT_ORIGIN@, LENGTH = @BOOTLOADER_PARTITION_SIZE@ - 0x20000
+    FLASH (rx) :    ORIGIN = @WOLFBOOT_ORIGIN@, LENGTH = @WOLFBOOT_KEYVAULT_ADDRESS@ - @ARCH_FLASH_OFFSET@
     RAM (rwx) :     ORIGIN = 0x30000000, LENGTH = 0x20000
     RAM_KV (rw):    ORIGIN = 0x30020000, LENGTH = 0x10000
     RAM_HEAP (rw):  ORIGIN = 0x30030000, LENGTH = 0x10000 /* 64KB Heap for wolfcrypt/PKCS11 */
-    FLASH_KEYVAULT(rw): ORIGIN = @WOLFBOOT_ORIGIN@ + LENGTH(FLASH), LENGTH = 0x1C000
-    FLASH_NSC(rx): ORIGIN = @WOLFBOOT_ORIGIN@ + LENGTH(FLASH) + LENGTH(FLASH_KEYVAULT), LENGTH = 0x4000
+    FLASH_KEYVAULT(rw): ORIGIN = @WOLFBOOT_KEYVAULT_ADDRESS@, LENGTH = @WOLFBOOT_KEYVAULT_SIZE@
+    FLASH_NSC(rx): ORIGIN = @WOLFBOOT_NSC_ADDRESS@, LENGTH = @WOLFBOOT_NSC_SIZE@
 }
 
 SECTIONS
diff --git a/hal/stm32l5.ld b/hal/stm32l5.ld
@@ -1,11 +1,11 @@
 MEMORY
 {
-    FLASH (rx) :    ORIGIN = @WOLFBOOT_ORIGIN@, LENGTH = @BOOTLOADER_PARTITION_SIZE@ - 0x20000
+    FLASH (rx) :    ORIGIN = @WOLFBOOT_ORIGIN@, LENGTH = @WOLFBOOT_KEYVAULT_ADDRESS@ - @ARCH_FLASH_OFFSET@
     RAM (rwx) :     ORIGIN = 0x30000000, LENGTH = 0x00012000
     RAM_HEAP (rw):  ORIGIN = 0x30012000, LENGTH = 0xc000 /* 49152 B Heap for wolfcrypt/PKCS11 */
     RAM_KV (rw):    ORIGIN = 0x3001e000, LENGTH = 0x2000
-    FLASH_KEYVAULT(rw): ORIGIN = @WOLFBOOT_ORIGIN@ + 0x20000, LENGTH = 0x18000
-    FLASH_NSC(rx): ORIGIN = @WOLFBOOT_ORIGIN@ + 0x38000, LENGTH = 0x8000
+    FLASH_KEYVAULT(rw): ORIGIN = @WOLFBOOT_KEYVAULT_ADDRESS@, LENGTH = @WOLFBOOT_KEYVAULT_SIZE@
+    FLASH_NSC(rx): ORIGIN = @WOLFBOOT_NSC_ADDRESS@, LENGTH = @WOLFBOOT_NSC_SIZE@
 }
 
 SECTIONS
diff --git a/hal/stm32u5.c b/hal/stm32u5.c
@@ -471,14 +471,22 @@ void RAMFUNCTION hal_flash_dualbank_swap(void)
 
 static void led_unsecure()
 {
-    uint32_t pin;
-
+#ifdef STM32_DISCOVERY
     /* Enable clock for User LED GPIOs */
     RCC_AHB2ENR1_CLOCK_ER|= GPIOH_AHB2ENR1_CLOCK_ER;
 
     /* Un-secure User LED GPIO pins */
-    GPIOH_SECCFGR&=~(1<<LED_USR_PIN);
-    GPIOH_SECCFGR&=~(1<<LED_BOOT_PIN);
+    GPIOH_SECCFGR &= ~(1 << LED_USR_PIN);
+    GPIOH_SECCFGR &= ~(1 << LED_BOOT_PIN);
+#else
+    /* Enable clock for User LED GPIOs */
+    RCC_AHB2ENR1_CLOCK_ER |= GPIOC_AHB2ENR1_CLOCK_ER;
+    RCC_AHB2ENR1_CLOCK_ER |= GPIOG_AHB2ENR1_CLOCK_ER;
+
+    /* Un-secure User LED GPIO pins */
+    GPIOG_SECCFGR &= ~(1 << LED_USR_PIN);
+    GPIOC_SECCFGR &= ~(1 << LED_BOOT_PIN);
+#endif
 }
 
 #if defined(DUALBANK_SWAP) && defined(__WOLFBOOT)
diff --git a/hal/stm32u5.h b/hal/stm32u5.h
@@ -248,14 +248,25 @@
 #define FLASH_OPTKEY2                         (0x4C5D6E7FU)
 
 /* GPIO*/
+#define GPIOC_BASE 0x52020800
+#define GPIOG_BASE 0x52021800
 #define GPIOH_BASE 0x52021C00
 
+#define GPIOC_SECCFGR (*(volatile uint32_t *)(GPIOC_BASE + 0x30))
+#define GPIOG_SECCFGR (*(volatile uint32_t *)(GPIOG_BASE + 0x30))
 #define GPIOH_SECCFGR (*(volatile uint32_t *)(GPIOH_BASE + 0x30))
 
+#ifdef STM32_DISCOVERY
 #define LED_BOOT_PIN (7) /* PH7 - Discovery - Green Led */
 #define LED_USR_PIN (6)  /* PH6 - Discovery  - Red Led */
+#else
+#define LED_BOOT_PIN (7) /* PC7 - Nucleo-U575ZI-Q - Green Led */
+#define LED_USR_PIN (2)  /* PG2 - Nucleo-U575ZI-Q - Red Led */
+#endif
 
 #define RCC_AHB2ENR1_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x8C ))
+#define GPIOC_AHB2ENR1_CLOCK_ER (1 << 2)
+#define GPIOG_AHB2ENR1_CLOCK_ER (1 << 6)
 #define GPIOH_AHB2ENR1_CLOCK_ER (1 << 7)
 #define TRNG_AHB2_CLOCK_ER      (1 << 18)
 
diff --git a/hal/stm32u5.ld b/hal/stm32u5.ld
@@ -1,11 +1,11 @@
 MEMORY
 {
-    FLASH (rx) :    ORIGIN = @WOLFBOOT_ORIGIN@, LENGTH = @BOOTLOADER_PARTITION_SIZE@ - 0x20000
+    FLASH (rx) :    ORIGIN = @WOLFBOOT_ORIGIN@, LENGTH = @WOLFBOOT_KEYVAULT_ADDRESS@ - @ARCH_FLASH_OFFSET@
     RAM (rwx) :     ORIGIN = 0x30000000, LENGTH = 0x00012000
     RAM_HEAP (rw):  ORIGIN = 0x30012000, LENGTH = 0xc000 /* 49152 B Heap for wolfcrypt/PKCS11 */
     RAM_KV (rw):    ORIGIN = 0x3001e000, LENGTH = 0x2000
-    FLASH_KEYVAULT(rw): ORIGIN = @WOLFBOOT_ORIGIN@ + 0x20000, LENGTH = 0x18000
-    FLASH_NSC(rx): ORIGIN = @WOLFBOOT_ORIGIN@ + 0x38000, LENGTH = 0x8000
+    FLASH_KEYVAULT(rw): ORIGIN = @WOLFBOOT_KEYVAULT_ADDRESS@, LENGTH = @WOLFBOOT_KEYVAULT_SIZE@
+    FLASH_NSC(rx): ORIGIN = @WOLFBOOT_NSC_ADDRESS@, LENGTH = @WOLFBOOT_NSC_SIZE@
 }
 
 SECTIONS
diff --git a/include/target.h.in b/include/target.h.in
@@ -49,12 +49,16 @@
     #include <stdint.h>
 
     /* linker script variables */
+    extern const uint32_t _wolfboot_nsc_address[];
+    extern const uint32_t _wolfboot_nsc_size[];
     extern const uint32_t _wolfboot_partition_boot_address[];
     extern const uint32_t _wolfboot_partition_size[];
     extern const uint32_t _wolfboot_partition_update_address[];
     extern const uint32_t _wolfboot_partition_swap_address[];
 
     /* create plain integers from linker script variables */
+    static const uint32_t WOLFBOOT_NSC_ADDRESS = (uint32_t)_wolfboot_nsc_address;
+    static const uint32_t WOLFBOOT_NSC_SIZE = (uint32_t)_wolfboot_nsc_size;
     static const uint32_t WOLFBOOT_PARTITION_BOOT_ADDRESS = (uint32_t)_wolfboot_partition_boot_address;
     static const uint32_t WOLFBOOT_PARTITION_SIZE = (uint32_t)_wolfboot_partition_size;
     static const uint32_t WOLFBOOT_PARTITION_UPDATE_ADDRESS = (uint32_t)_wolfboot_partition_update_address;
@@ -73,6 +77,12 @@
     #endif
 
     /* use values provided on input template parsing */
+    #ifndef WOLFBOOT_NSC_ADDRESS
+    #define WOLFBOOT_NSC_ADDRESS              @WOLFBOOT_NSC_ADDRESS@
+    #endif
+    #ifndef WOLFBOOT_NSC_SIZE
+    #define WOLFBOOT_NSC_SIZE                 @WOLFBOOT_NSC_SIZE@
+    #endif
     #ifndef WOLFBOOT_PARTITION_BOOT_ADDRESS
     #define WOLFBOOT_PARTITION_BOOT_ADDRESS   @WOLFBOOT_PARTITION_BOOT_ADDRESS@
     #endif
diff --git a/test-app/ARM-stm32u5-ns.ld b/test-app/ARM-stm32u5-ns.ld
@@ -1,7 +1,7 @@
 MEMORY
 {
     FLASH (rx) : ORIGIN = @WOLFBOOT_TEST_APP_ADDRESS@, LENGTH = @WOLFBOOT_TEST_APP_SIZE@
-    RAM (rwx) : ORIGIN = 0x20040000, LENGTH = 64K /* Run in lowmem */
+    RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 128K
 }
 
 SECTIONS
diff --git a/test-app/app_stm32u5.c b/test-app/app_stm32u5.c
@@ -30,20 +30,36 @@
 #include "wolfboot/wolfboot.h"
 #include "target.h"
 
+#ifdef STM32_DISCOVERY
 #define LED_BOOT_PIN (7) /* PH7 - Discovery - Green Led */
-#define LED_USR_PIN  (6) /* PH6 - Discovery - Red Led */
+#define LED_USR_PIN (6)  /* PH6 - Discovery  - Red Led */
+#else
+#define LED_BOOT_PIN (7) /* PC7 - Nucleo-U575ZI-Q - Green Led */
+#define LED_USR_PIN (2)  /* PG2 - Nucleo-U575ZI-Q - Red Led */
+#endif
 
 /*Non-Secure */
 #define RCC_BASE            (0x46020C00)   /* RM0456 - Table 4 */
 #define PWR_BASE            (0x46020800)   /* RM0456 - Table 4 */
+#define GPIOC_BASE 0x42020800
+#define GPIOG_BASE 0x42021800
 #define GPIOH_BASE 0x42021C00
 
+#define GPIOC_MODER (*(volatile uint32_t *)(GPIOC_BASE + 0x00))
+#define GPIOC_PUPDR (*(volatile uint32_t *)(GPIOC_BASE + 0x0C))
+#define GPIOC_BSRR  (*(volatile uint32_t *)(GPIOC_BASE + 0x18))
+
+#define GPIOG_MODER (*(volatile uint32_t *)(GPIOG_BASE + 0x00))
+#define GPIOG_PUPDR (*(volatile uint32_t *)(GPIOG_BASE + 0x0C))
+#define GPIOG_BSRR  (*(volatile uint32_t *)(GPIOG_BASE + 0x18))
 
-#define GPIOH_MODER (*(volatile uint32_t *)(GPIOH_BASE + 0x00)) 
-#define GPIOH_PUPDR (*(volatile uint32_t *)(GPIOH_BASE + 0x0C)) 
-#define GPIOH_BSRR  (*(volatile uint32_t *)(GPIOH_BASE + 0x18)) 
+#define GPIOH_MODER (*(volatile uint32_t *)(GPIOH_BASE + 0x00))
+#define GPIOH_PUPDR (*(volatile uint32_t *)(GPIOH_BASE + 0x0C))
+#define GPIOH_BSRR  (*(volatile uint32_t *)(GPIOH_BASE + 0x18))
 
 #define RCC_AHB2ENR1_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x8C ))
+#define GPIOC_AHB2ENR1_CLOCK_ER (1 << 2)
+#define GPIOG_AHB2ENR1_CLOCK_ER (1 << 6)
 #define GPIOH_AHB2ENR1_CLOCK_ER (1 << 7)
 
 #define PWR_CR2              (*(volatile uint32_t *)(PWR_BASE + 0x04))
@@ -54,7 +70,11 @@ static void boot_led_on(void)
     uint32_t reg;
     uint32_t pin = LED_BOOT_PIN;
 
+#ifdef STM32_DISCOVERY
     RCC_AHB2ENR1_CLOCK_ER|= GPIOH_AHB2ENR1_CLOCK_ER;
+#else
+    RCC_AHB2ENR1_CLOCK_ER|= GPIOC_AHB2ENR1_CLOCK_ER;
+#endif
     /* Delay after an RCC peripheral clock enabling */
     reg = RCC_AHB2ENR1_CLOCK_ER;
 
@@ -63,35 +83,61 @@ static void boot_led_on(void)
     PWR_CR2 |= PWR_CR2_IOSV;
 #endif
 
+#ifdef STM32_DISCOVERY
     reg = GPIOH_MODER & ~(0x03 << (pin * 2));
     GPIOH_MODER = reg | (1 << (pin * 2));
     GPIOH_PUPDR &= ~(0x03 << (pin * 2));
     GPIOH_BSRR |= (1 << (pin + 16));
+#else
+    reg = GPIOC_MODER & ~(0x03 << (pin * 2));
+    GPIOC_MODER = reg | (1 << (pin * 2));
+    GPIOC_PUPDR &= ~(0x03 << (pin * 2));
+    GPIOC_BSRR |= (1 << pin);
+#endif
 }
 
 static void boot_led_off(void)
 {
+#ifdef STM32_DISCOVERY
     GPIOH_BSRR |= (1 << (LED_BOOT_PIN));
+#else
+    GPIOC_BSRR |= (1 << (LED_BOOT_PIN + 16));
+#endif
 }
 
 void usr_led_on(void)
 {
     uint32_t reg;
     uint32_t pin = LED_USR_PIN;
 
+#ifdef STM32_DISCOVERY
     RCC_AHB2ENR1_CLOCK_ER|= GPIOH_AHB2ENR1_CLOCK_ER;
+#else
+    RCC_AHB2ENR1_CLOCK_ER|= GPIOG_AHB2ENR1_CLOCK_ER;
+#endif
     /* Delay after an RCC peripheral clock enabling */
     reg = RCC_AHB2ENR1_CLOCK_ER;
 
+#ifdef STM32_DISCOVERY
     reg = GPIOH_MODER & ~(0x03 << (pin * 2));
     GPIOH_MODER = reg | (1 << (pin * 2));
     GPIOH_PUPDR &= ~(0x03 << (pin * 2));
     GPIOH_BSRR |= (1 << (pin + 16));
+#else
+    reg = GPIOG_MODER & ~(0x03 << (pin * 2));
+    GPIOG_MODER = reg | (1 << (pin * 2));
+    GPIOG_PUPDR &= ~(0x03 << (pin * 2));
+    GPIOG_BSRR |= (1 << pin);
+#endif
 }
 
 void usr_led_off(void)
 {
+#ifdef STM32_DISCOVERY
     GPIOH_BSRR |= (1 << (LED_USR_PIN));
+#else
+    GPIOG_BSRR |= (1 << (LED_USR_PIN + 16));
+#endif
 }
 
 void main(void)
diff --git a/tools/scripts/set-stm32-tz-option-bytes.sh b/tools/scripts/set-stm32-tz-option-bytes.sh
