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| 1 | +/* mcxa.c |
| 2 | + * |
| 3 | + * Copyright (C) 2021 wolfSSL Inc. |
| 4 | + * |
| 5 | + * This file is part of wolfBoot. |
| 6 | + * |
| 7 | + * wolfBoot is free software; you can redistribute it and/or modify |
| 8 | + * it under the terms of the GNU General Public License as published by |
| 9 | + * the Free Software Foundation; either version 2 of the License, or |
| 10 | + * (at your option) any later version. |
| 11 | + * |
| 12 | + * wolfBoot is distributed in the hope that it will be useful, |
| 13 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | + * GNU General Public License for more details. |
| 16 | + * |
| 17 | + * You should have received a copy of the GNU General Public License |
| 18 | + * along with this program; if not, write to the Free Software |
| 19 | + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA |
| 20 | + */ |
| 21 | + |
| 22 | +#include <stdint.h> |
| 23 | +#include <target.h> |
| 24 | +#include "image.h" |
| 25 | +/* FSL includes */ |
| 26 | +#include "fsl_common.h" |
| 27 | + |
| 28 | +/* Clock + RAM voltage settings */ |
| 29 | +#include "fsl_clock.h" |
| 30 | +#include "fsl_spc.h" |
| 31 | + |
| 32 | +/* Flash driver */ |
| 33 | +#include "fsl_romapi.h" |
| 34 | + |
| 35 | +#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ |
| 36 | + |
| 37 | +static flash_config_t pflash; |
| 38 | +//static ftfx_cache_config_t pcache; |
| 39 | +static int flash_init = 0; |
| 40 | + |
| 41 | +#ifdef __WOLFBOOT |
| 42 | +/* Assert hook needed by Kinetis SDK */ |
| 43 | +void __assert_func(const char *a, int b, const char *c, const char *d) |
| 44 | +{ |
| 45 | + while(1) |
| 46 | + ; |
| 47 | +} |
| 48 | + |
| 49 | +/* The following clock setting function is autogenerated by the MCUXpresso IDE */ |
| 50 | +void BOARD_BootClockFRO96M(void) |
| 51 | +{ |
| 52 | + uint32_t coreFreq; |
| 53 | + spc_active_mode_core_ldo_option_t ldoOption; |
| 54 | + spc_sram_voltage_config_t sramOption; |
| 55 | + |
| 56 | + /* Get the CPU Core frequency */ |
| 57 | + coreFreq = CLOCK_GetCoreSysClkFreq(); |
| 58 | + |
| 59 | + /* The flow of increasing voltage and frequency */ |
| 60 | + if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) { |
| 61 | + /* Set the LDO_CORE VDD regulator level */ |
| 62 | + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; |
| 63 | + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; |
| 64 | + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); |
| 65 | + /* Configure Flash to support different voltage level and frequency */ |
| 66 | + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U)); |
| 67 | + /* Specifies the operating voltage for the SRAM's read/write timing margin */ |
| 68 | + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; |
| 69 | + sramOption.requestVoltageUpdate = true; |
| 70 | + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); |
| 71 | + } |
| 72 | + |
| 73 | + CLOCK_SetupFROHFClocking(96000000U); /*!< Enable FRO HF(96MHz) output */ |
| 74 | + |
| 75 | + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ |
| 76 | + |
| 77 | + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ |
| 78 | + |
| 79 | + /* The flow of decreasing voltage and frequency */ |
| 80 | + if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) { |
| 81 | + /* Configure Flash to support different voltage level and frequency */ |
| 82 | + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U)); |
| 83 | + /* Specifies the operating voltage for the SRAM's read/write timing margin */ |
| 84 | + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; |
| 85 | + sramOption.requestVoltageUpdate = true; |
| 86 | + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); |
| 87 | + /* Set the LDO_CORE VDD regulator level */ |
| 88 | + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; |
| 89 | + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; |
| 90 | + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); |
| 91 | + } |
| 92 | + |
| 93 | + /*!< Set up clock selectors - Attach clocks to the peripheries */ |
| 94 | + |
| 95 | + /*!< Set up dividers */ |
| 96 | + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ |
| 97 | + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ |
| 98 | +} |
| 99 | + |
| 100 | + |
| 101 | +void hal_init(void) |
| 102 | +{ |
| 103 | + /* Clock setting */ |
| 104 | + BOARD_BootClockFRO96M(); |
| 105 | + |
| 106 | + /* Clear the FLASH configuration structure */ |
| 107 | + memset(&pflash, 0, sizeof(pflash)); |
| 108 | + /* FLASH driver init */ |
| 109 | + FLASH_Init(&pflash); |
| 110 | +} |
| 111 | + |
| 112 | +void hal_prepare_boot(void) |
| 113 | +{ |
| 114 | +} |
| 115 | + |
| 116 | + |
| 117 | +#endif |
| 118 | + |
| 119 | +int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len) |
| 120 | +{ |
| 121 | + int w = 0; |
| 122 | + int ret; |
| 123 | + const uint8_t empty_qword[16] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, |
| 124 | + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; |
| 125 | + |
| 126 | + while (len > 0) { |
| 127 | + if ((len < 16) || address & 0x0F) { |
| 128 | + uint8_t aligned_qword[16]; |
| 129 | + uint32_t address_align = address - (address & 0x0F); |
| 130 | + uint32_t start_off = address - address_align; |
| 131 | + int i; |
| 132 | + memcpy(aligned_qword, (void*)address_align, 16); |
| 133 | + for (i = start_off; ((i < 16) && (i < len + (int)start_off)); i++) |
| 134 | + aligned_qword[i] = data[w++]; |
| 135 | + if (memcmp(aligned_qword, empty_qword, 16) != 0) { |
| 136 | + ret = FLASH_ProgramPhrase(&pflash, address_align, aligned_qword, 16); |
| 137 | + if (ret != kStatus_Success) |
| 138 | + return -1; |
| 139 | + } |
| 140 | + address += i; |
| 141 | + len -= i; |
| 142 | + } else { |
| 143 | + uint32_t len_align = len - (len & 0x0F); |
| 144 | + ret = FLASH_ProgramPhrase(&pflash, address, (uint8_t*)data + w, len_align); |
| 145 | + if (ret != kStatus_Success) |
| 146 | + return -1; |
| 147 | + len -= len_align; |
| 148 | + address += len_align; |
| 149 | + } |
| 150 | + } |
| 151 | + return 0; |
| 152 | +} |
| 153 | + |
| 154 | +void RAMFUNCTION hal_flash_unlock(void) |
| 155 | +{ |
| 156 | +} |
| 157 | + |
| 158 | +void RAMFUNCTION hal_flash_lock(void) |
| 159 | +{ |
| 160 | +} |
| 161 | + |
| 162 | + |
| 163 | +int RAMFUNCTION hal_flash_erase(uint32_t address, int len) |
| 164 | +{ |
| 165 | + while ((address % 4) != 0) |
| 166 | + address --; |
| 167 | + if (FLASH_EraseSector(&pflash, address, len, kFLASH_ApiEraseKey) != kStatus_Success) |
| 168 | + return -1; |
| 169 | + return 0; |
| 170 | +} |
| 171 | + |
| 172 | + |
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