hal: stm32u5: Fix FLASH_CR_PNB_MASK

This commit update the PNB (Secure page number selection) mask according to reference manual update.
In RM0456 document update (Rev.3 -> Rev.4), PNB bits in FLASH_SECCR (Section 7.9.10) has been updated from 7 bits to 8 bits for the support of 2MB in single bank.
Logically, devices which flash is lesser than 2MB will ignore bit 10 because of the definition (Reserved). However, for other devices, NUCLEO-U5A5ZJ-Q for example, page calculation will be wrong because bit 10 is __always 1__ after flipping by:

	reg = *cr & (~((FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT) | FLASH_CR_BKER));

Without this commit, some devices will be failed to erase pages of flash, and lead to update failure.

Signed-off-by: Elwin Huang <[email protected]>

Author: s09289728096

hal/stm32u5.h

@@ -210,7 +210,7 @@
 #define FLASH_CR_PER                        (1 << 1)
 #define FLASH_CR_MER1                       (1 << 2)
 #define FLASH_CR_PNB_SHIFT                  3
-#define FLASH_CR_PNB_MASK                   0x7F
+#define FLASH_CR_PNB_MASK                   0xFF	/* RM0456 - Table 79 */
 #define FLASH_CR_BKER                       (1 << 11)
 #define FLASH_CR_MER2                       (1 << 15)
 #define FLASH_CR_STRT                       (1 << 16)