diff --git a/STM32G0_Nucleo/Core/Inc/main.h b/STM32G0_Nucleo/Core/Inc/main.h new file mode 100644 index 0000000..1c21925 --- /dev/null +++ b/STM32G0_Nucleo/Core/Inc/main.h @@ -0,0 +1,79 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" +#include "stm32g0xx_ll_iwdg.h" +#include "stm32g0xx_ll_bus.h" +#include "stm32g0xx_ll_cortex.h" +#include "stm32g0xx_ll_rcc.h" +#include "stm32g0xx_ll_system.h" +#include "stm32g0xx_ll_utils.h" +#include "stm32g0xx_ll_pwr.h" +#include "stm32g0xx_ll_gpio.h" +#include "stm32g0xx_ll_dma.h" + +#include "stm32g0xx_ll_exti.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/STM32G0_Nucleo/Core/Inc/stm32_assert.h b/STM32G0_Nucleo/Core/Inc/stm32_assert.h new file mode 100644 index 0000000..c096d4b --- /dev/null +++ b/STM32G0_Nucleo/Core/Inc/stm32_assert.h @@ -0,0 +1,53 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32_assert.h + * @brief STM32 assert file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_ASSERT_H +#define __STM32_ASSERT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Includes ------------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_ASSERT_H */ + diff --git a/STM32G0_Nucleo/Core/Inc/stm32g0xx_hal_conf.h b/STM32G0_Nucleo/Core/Inc/stm32g0xx_hal_conf.h new file mode 100644 index 0000000..4df19d4 --- /dev/null +++ b/STM32G0_Nucleo/Core/Inc/stm32g0xx_hal_conf.h @@ -0,0 +1,351 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g0xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_CONF_H +#define STM32G0xx_HAL_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_COMP_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_EXTI_MODULE_ENABLED */ +/* #define HAL_FDCAN_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_I2C_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +/* #define HAL_UART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Register Callbacks selection ############################## */ +/** + * @brief This is the list of modules where register callback can be used + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0u +#define USE_HAL_CEC_REGISTER_CALLBACKS 0u +#define USE_HAL_COMP_REGISTER_CALLBACKS 0u +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0u +#define USE_HAL_DAC_REGISTER_CALLBACKS 0u +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0u +#define USE_HAL_HCD_REGISTER_CALLBACKS 0u +#define USE_HAL_I2C_REGISTER_CALLBACKS 0u +#define USE_HAL_I2S_REGISTER_CALLBACKS 0u +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0u +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0u +#define USE_HAL_PCD_REGISTER_CALLBACKS 0u +#define USE_HAL_RNG_REGISTER_CALLBACKS 0u +#define USE_HAL_RTC_REGISTER_CALLBACKS 0u +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0u +#define USE_HAL_SPI_REGISTER_CALLBACKS 0u +#define USE_HAL_TIM_REGISTER_CALLBACKS 0u +#define USE_HAL_UART_REGISTER_CALLBACKS 0u +#define USE_HAL_USART_REGISTER_CALLBACKS 0u +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0u + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined (HSI48_VALUE) + #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ +#endif + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz +The real value may vary depending on the variations +in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S1 peripheral + * This value is used by the RCC HAL module to compute the I2S1 clock source + * frequency. + */ +#if !defined (EXTERNAL_I2S1_CLOCK_VALUE) +#define EXTERNAL_I2S1_CLOCK_VALUE (48000UL) /*!< Value of the I2S1 External clock source in Hz*/ +#endif /* EXTERNAL_I2S1_CLOCK_VALUE */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief External clock source for I2S2 peripheral + * This value is used by the RCC HAL module to compute the I2S2 clock source + * frequency. + */ +#if !defined (EXTERNAL_I2S2_CLOCK_VALUE) + #define EXTERNAL_I2S2_CLOCK_VALUE 48000U /*!< Value of the I2S2 External clock source in Hz*/ +#endif /* EXTERNAL_I2S2_CLOCK_VALUE */ +#endif + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 3U /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* ################## CRYP peripheral configuration ########################## */ + +#define USE_HAL_CRYP_SUSPEND_RESUME 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include modules header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32g0xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32g0xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32g0xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32g0xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32g0xx_hal_adc.h" +#include "stm32g0xx_hal_adc_ex.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED +#include "stm32g0xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED +#include "stm32g0xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32g0xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32g0xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED +#include "stm32g0xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32g0xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED +#include "stm32g0xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED +#include "stm32g0xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED +#include "stm32g0xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32g0xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED +#include "stm32g0xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32g0xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32g0xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32g0xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32g0xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32g0xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32g0xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32g0xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32g0xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32g0xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32g0xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32g0xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32g0xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32g0xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32g0xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for functions parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_CONF_H */ diff --git a/STM32G0_Nucleo/Core/Inc/stm32g0xx_it.h b/STM32G0_Nucleo/Core/Inc/stm32g0xx_it.h new file mode 100644 index 0000000..85f02da --- /dev/null +++ b/STM32G0_Nucleo/Core/Inc/stm32g0xx_it.h @@ -0,0 +1,62 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g0xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32G0xx_IT_H +#define __STM32G0xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32G0xx_IT_H */ diff --git a/STM32G0_Nucleo/Core/Inc/user_settings.h b/STM32G0_Nucleo/Core/Inc/user_settings.h new file mode 100644 index 0000000..20f6146 --- /dev/null +++ b/STM32G0_Nucleo/Core/Inc/user_settings.h @@ -0,0 +1,653 @@ +/** + ****************************************************************************** + * File Name : wolfSSL.I-CUBE-wolfSSL_conf.h + * Description : This file provides code for the configuration + * of the wolfSSL.I-CUBE-wolfSSL_conf.h instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __WOLFSSL_I_CUBE_WOLFSSL_CONF_H__ +#define __WOLFSSL_I_CUBE_WOLFSSL_CONF_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +/** + MiddleWare name : wolfSSL.I-CUBE-wolfSSL.5.5.4 + MiddleWare fileName : wolfSSL.I-CUBE-wolfSSL_conf.h + MiddleWare version : +*/ +/*---------- WOLF_CONF_DEBUG -----------*/ +#define WOLF_CONF_DEBUG 1 + +/*---------- WOLF_CONF_WOLFCRYPT_ONLY -----------*/ +#define WOLF_CONF_WOLFCRYPT_ONLY 1 + +/*---------- WOLF_CONF_TLS13 -----------*/ +#define WOLF_CONF_TLS13 1 + +/*---------- WOLF_CONF_TLS12 -----------*/ +#define WOLF_CONF_TLS12 1 + +/*---------- WOLF_CONF_DTLS -----------*/ +#define WOLF_CONF_DTLS 0 + +/*---------- WOLF_CONF_MATH -----------*/ +#define WOLF_CONF_MATH 1 + +/*---------- WOLF_CONF_RTOS -----------*/ +#define WOLF_CONF_RTOS 1 + +/*---------- WOLF_CONF_RNG -----------*/ +#define WOLF_CONF_RNG 0 + +/*---------- WOLF_CONF_RSA -----------*/ +#define WOLF_CONF_RSA 0 + +/*---------- WOLF_CONF_ECC -----------*/ +#define WOLF_CONF_ECC 0 + +/*---------- WOLF_CONF_DH -----------*/ +#define WOLF_CONF_DH 0 + +/*---------- WOLF_CONF_AESGCM -----------*/ +#define WOLF_CONF_AESGCM 0 + +/*---------- WOLF_CONF_AESCBC -----------*/ +#define WOLF_CONF_AESCBC 1 + +/*---------- WOLF_CONF_CHAPOLY -----------*/ +#define WOLF_CONF_CHAPOLY 1 + +/*---------- WOLF_CONF_EDCURVE25519 -----------*/ +#define WOLF_CONF_EDCURVE25519 0 + +/*---------- WOLF_CONF_MD5 -----------*/ +#define WOLF_CONF_MD5 1 + +/*---------- WOLF_CONF_SHA1 -----------*/ +#define WOLF_CONF_SHA1 0 + +/*---------- WOLF_CONF_SHA2_224 -----------*/ +#define WOLF_CONF_SHA2_224 0 + +/*---------- WOLF_CONF_SHA2_256 -----------*/ +#define WOLF_CONF_SHA2_256 1 + +/*---------- WOLF_CONF_SHA2_384 -----------*/ +#define WOLF_CONF_SHA2_384 0 + +/*---------- WOLF_CONF_SHA2_512 -----------*/ +#define WOLF_CONF_SHA2_512 0 + +/*---------- WOLF_CONF_SHA3 -----------*/ +#define WOLF_CONF_SHA3 0 + +/*---------- WOLF_CONF_PSK -----------*/ +#define WOLF_CONF_PSK 1 + +/*---------- WOLF_CONF_PWDBASED -----------*/ +#define WOLF_CONF_PWDBASED 1 + +/*---------- WOLF_CONF_KEEP_PEER_CERT -----------*/ +#define WOLF_CONF_KEEP_PEER_CERT 1 + +/*---------- WOLF_CONF_BASE64_ENCODE -----------*/ +#define WOLF_CONF_BASE64_ENCODE 1 + +/*---------- WOLF_CONF_OPENSSL_EXTRA -----------*/ +#define WOLF_CONF_OPENSSL_EXTRA 2 + +/*---------- WOLF_CONF_TEST -----------*/ +#define WOLF_CONF_TEST 1 + +/*---------- WOLF_CONF_PQM4 -----------*/ +#define WOLF_CONF_PQM4 0 + +/* ------------------------------------------------------------------------- */ +/* Hardware platform */ +/* ------------------------------------------------------------------------- */ +#define NO_STM32_HASH +#define NO_STM32_CRYPTO + +#if defined(STM32WB55xx) + #define WOLFSSL_STM32WB + #define WOLFSSL_STM32_PKA + #undef NO_STM32_CRYPTO + #define HAL_CONSOLE_UART huart1 +#elif defined(STM32F407xx) + #define WOLFSSL_STM32F4 + #define HAL_CONSOLE_UART huart2 +#elif defined(STM32F437xx) + #define WOLFSSL_STM32F4 + #undef NO_STM32_HASH + #undef NO_STM32_CRYPTO + #define STM32_HAL_V2 + #define HAL_CONSOLE_UART huart4 +#elif defined(STM32F777xx) + #define WOLFSSL_STM32F7 + #undef NO_STM32_HASH + #undef NO_STM32_CRYPTO + #define STM32_HAL_V2 + #define HAL_CONSOLE_UART huart2 +#elif defined(STM32F756xx) + #define WOLFSSL_STM32F7 + #undef NO_STM32_HASH + #undef NO_STM32_CRYPTO + #define STM32_HAL_V2 + #define HAL_CONSOLE_UART huart3 +#elif defined(STM32H753xx) + #define WOLFSSL_STM32H7 + #undef NO_STM32_HASH + #undef NO_STM32_CRYPTO + #define HAL_CONSOLE_UART huart3 +#elif defined(STM32L4A6xx) + #define WOLFSSL_STM32L4 + #undef NO_STM32_HASH + #undef NO_STM32_CRYPTO + #define HAL_CONSOLE_UART hlpuart1 +#elif defined(STM32L475xx) + #define WOLFSSL_STM32L4 + #define HAL_CONSOLE_UART huart1 +#elif defined(STM32L562xx) + #define WOLFSSL_STM32L5 + #define WOLFSSL_STM32_PKA + #undef NO_STM32_HASH + #undef NO_STM32_CRYPTO + #define HAL_CONSOLE_UART huart1 +#elif defined(STM32L552xx) + #define WOLFSSL_STM32L5 + #undef NO_STM32_HASH + #define HAL_CONSOLE_UART hlpuart1 +#elif defined(STM32F207xx) + #define WOLFSSL_STM32F2 + #define HAL_CONSOLE_UART huart3 +#elif defined(STM32F217xx) + #define WOLFSSL_STM32F2 + #define HAL_CONSOLE_UART huart2 +#elif defined(STM32F107xC) + #define WOLFSSL_STM32F1 + #define HAL_CONSOLE_UART huart4 + #define NO_STM32_RNG +#elif defined(STM32F401xE) + #define WOLFSSL_STM32F4 + #define HAL_CONSOLE_UART huart2 + #define NO_STM32_RNG + #define WOLFSSL_GENSEED_FORTEST +#elif defined(STM32G071xx) + #define WOLFSSL_STM32G0 + #define HAL_CONSOLE_UART huart2 + #define NO_STM32_RNG + #define WOLFSSL_GENSEED_FORTEST +#elif defined(STM32U575xx) || defined(STM32U585xx) + #define HAL_CONSOLE_UART huart1 + #define WOLFSSL_STM32U5 + #define STM32_HAL_V2 + #ifdef STM32U585xx + #undef NO_STM32_HASH + #undef NO_STM32_CRYPTO + #define WOLFSSL_STM32_PKA + #endif +#else +// #warning Please define a hardware platform! + /* This means there is not a pre-defined platform for your board/CPU */ + /* You need to define a CPU type, HW crypto and debug UART */ + /* CPU Type: WOLFSSL_STM32F1, WOLFSSL_STM32F2, WOLFSSL_STM32F4, + WOLFSSL_STM32F7, WOLFSSL_STM32H7, WOLFSSL_STM32L4, WOLFSSL_STM32L5, + WOLFSSL_STM32G0, WOLFSSL_STM32WB and WOLFSSL_STM32U5 */ + #define WOLFSSL_STM32G0 + + /* Debug UART used for printf */ + /* The UART interface number varies for each board/CPU */ + /* Typically this is the UART attached to the ST-Link USB CDC UART port */ + // #define HAL_CONSOLE_UART huart4 + + /* Hardware Crypto - uncomment as available on hardware */ + //#define WOLFSSL_STM32_PKA + //#define NO_STM32_RNG + #define NO_STM32_HASH + #define NO_STM32_CRYPTO + // #define WOLF_CRYPTO_CB + //#define WOLFSSL_GENSEED_FORTEST /* if no HW RNG is available use test seed */ + //#define STM32_HAL_V2 +#endif + +/* ------------------------------------------------------------------------- */ +/* Platform */ +/* ------------------------------------------------------------------------- */ +#define SIZEOF_LONG_LONG 8 +#define WOLFSSL_GENERAL_ALIGNMENT 4 +#define WOLFSSL_STM32_CUBEMX +#define WOLFSSL_SMALL_STACK +#define WOLFSSL_USER_IO +#define WOLFSSL_NO_SOCK +#define WOLFSSL_IGNORE_FILE_WARN + +/* ------------------------------------------------------------------------- */ +/* Operating System */ +/* ------------------------------------------------------------------------- */ +#if defined(WOLF_CONF_RTOS) && WOLF_CONF_RTOS == 2 + #define FREERTOS +#else + #define SINGLE_THREADED +#endif + +/* ------------------------------------------------------------------------- */ +/* Math Configuration */ +/* ------------------------------------------------------------------------- */ +/* 1=Fast (stack) + * 2=Normal (heap) + * 3=Single Precision C (only common curves/key sizes) + * 4=Single Precision ASM Cortex-M3+ + * 5=Single Precision ASM Cortex-M0 (Generic Thumb) + * 6=Single Precision C all small + * 7=Single Precision C all big + */ +#if defined(WOLF_CONF_MATH) && WOLF_CONF_MATH == 1 + /* fast (stack) math - tfm.c */ + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT + + /* Optimizations (TFM_ARM, TFM_ASM or none) */ + //#define TFM_NO_ASM + //#define TFM_ASM +#elif defined(WOLF_CONF_MATH) && WOLF_CONF_MATH == 2 + /* heap math - integer.c */ + #define USE_INTEGER_HEAP_MATH +#elif defined(WOLF_CONF_MATH) && (WOLF_CONF_MATH >= 3) + /* single precision only */ + #define WOLFSSL_SP + #if WOLF_CONF_MATH != 7 + #define WOLFSSL_SP_SMALL /* use smaller version of code */ + #endif + #if defined(WOLF_CONF_RSA) && WOLF_CONF_RSA == 1 + #define WOLFSSL_HAVE_SP_RSA + #endif + #if defined(WOLF_CONF_DH) && WOLF_CONF_DH == 1 + #define WOLFSSL_HAVE_SP_DH + #endif + #if defined(WOLF_CONF_ECC) && WOLF_CONF_ECC == 1 + #define WOLFSSL_HAVE_SP_ECC + #endif + #if WOLF_CONF_MATH == 6 || WOLF_CONF_MATH == 7 + #define WOLFSSL_SP_MATH /* disable non-standard curves / key sizes */ + #endif + #define SP_WORD_SIZE 32 + + /* Enable to put all math on stack (no heap) */ + //#define WOLFSSL_SP_NO_MALLOC + /* Enable for SP cache resistance (not usually enabled for embedded micros) */ + //#define WOLFSSL_SP_CACHE_RESISTANT + + #if WOLF_CONF_MATH == 4 || WOLF_CONF_MATH == 5 + #define WOLFSSL_SP_ASM /* required if using the ASM versions */ + #if WOLF_CONF_MATH == 4 + /* ARM Cortex-M3+ */ + #define WOLFSSL_SP_ARM_CORTEX_M_ASM + #endif + #if WOLF_CONF_MATH == 5 + /* Generic ARM Thumb (Cortex-M0) Assembly */ + #define WOLFSSL_SP_ARM_THUMB_ASM + #endif + #endif +#endif + +/* ------------------------------------------------------------------------- */ +/* Enable Features */ +/* ------------------------------------------------------------------------- */ +/* Required for TLS */ +#define HAVE_TLS_EXTENSIONS +#define HAVE_SUPPORTED_CURVES +#define HAVE_ENCRYPT_THEN_MAC +#define HAVE_EXTENDED_MASTER + +#if defined(WOLF_CONF_TLS13) && WOLF_CONF_TLS13 == 1 + #define WOLFSSL_TLS13 + #define HAVE_HKDF +#endif +#if defined(WOLF_CONF_DTLS) && WOLF_CONF_DTLS == 1 + #define WOLFSSL_DTLS +#endif +#if defined(WOLF_CONF_PSK) && WOLF_CONF_PSK == 0 + #define NO_PSK +#endif +#if defined(WOLF_CONF_PWDBASED) && WOLF_CONF_PWDBASED == 0 + #define NO_PWDBASED +#endif +#if defined(WOLF_CONF_KEEP_PEER_CERT) && WOLF_CONF_KEEP_PEER_CERT == 1 + #define KEEP_PEER_CERT +#endif +#if defined(WOLF_CONF_BASE64_ENCODE) && WOLF_CONF_BASE64_ENCODE == 1 + #define WOLFSSL_BASE64_ENCODE +#endif +#if defined(WOLF_CONF_OPENSSL_EXTRA) && WOLF_CONF_OPENSSL_EXTRA >= 1 + #define OPENSSL_EXTRA + #if !defined(INT_MAX) + #include + #endif +#endif +#if defined(WOLF_CONF_OPENSSL_EXTRA) && WOLF_CONF_OPENSSL_EXTRA >= 2 + #define OPENSSL_ALL +#endif + +/* TLS Session Cache */ +#if 0 + #define SMALL_SESSION_CACHE +#else + #define NO_SESSION_CACHE +#endif + +/* Post Quantum + * Note: PQM4 is compatible with STM32. The project can be found at: + * https://github.com/mupq/pqm4 + */ +#if defined(WOLF_CONF_PQM4) && WOLF_CONF_PQM4 == 1 + #define HAVE_PQM4 +#endif + +/* ------------------------------------------------------------------------- */ +/* Crypto */ +/* ------------------------------------------------------------------------- */ +/* RSA */ +#undef NO_RSA +#if defined(WOLF_CONF_RSA) && WOLF_CONF_RSA == 1 + #ifdef USE_FAST_MATH + /* Maximum math bits (Max RSA key bits * 2) */ + #undef FP_MAX_BITS + #define FP_MAX_BITS 4096 + #endif + + /* half as much memory but twice as slow */ + #undef RSA_LOW_MEM + //#define RSA_LOW_MEM + + /* Enables blinding mode, to prevent timing attacks */ + #undef WC_RSA_BLINDING + #define WC_RSA_BLINDING + + /* RSA PSS Support (required for TLS v1.3) */ + #ifdef WOLFSSL_TLS13 + #define WC_RSA_PSS + #endif +#else + #define NO_RSA +#endif + +/* ECC */ +#undef HAVE_ECC +#if defined(WOLF_CONF_ECC) && WOLF_CONF_ECC == 1 + #define HAVE_ECC + + /* Manually define enabled curves */ + #define ECC_USER_CURVES + + //#define HAVE_ECC192 + //#define HAVE_ECC224 + #undef NO_ECC256 + //#define HAVE_ECC384 + //#define HAVE_ECC521 + + /* Fixed point cache (speeds repeated operations against same private key) */ + #undef FP_ECC + //#define FP_ECC + #ifdef FP_ECC + /* Bits / Entries */ + #undef FP_ENTRIES + #define FP_ENTRIES 2 + #undef FP_LUT + #define FP_LUT 4 + #endif + + /* Optional ECC calculation method */ + /* Note: doubles heap usage, but slightly faster */ + #undef ECC_SHAMIR + #define ECC_SHAMIR + + /* Reduces heap usage, but slower */ + #define ECC_TIMING_RESISTANT + + /* Compressed ECC key support */ + //#define HAVE_COMP_KEY + + #ifdef USE_FAST_MATH + #ifdef NO_RSA + /* Custom fastmath size if not using RSA */ + /* MAX = ROUND32(ECC BITS) * 2 */ + #define FP_MAX_BITS (256 * 2) + #else + #define ALT_ECC_SIZE + #endif + + /* Enable TFM optimizations for ECC */ + //#define TFM_ECC192 + //#define TFM_ECC224 + //#define TFM_ECC256 + //#define TFM_ECC384 + //#define TFM_ECC521 + #endif +#endif + +/* DH */ +#undef NO_DH +#if defined(WOLF_CONF_DH) && WOLF_CONF_DH == 1 + #define HAVE_DH /* freeRTOS settings.h requires this */ + #define HAVE_FFDHE_2048 + #define HAVE_DH_DEFAULT_PARAMS +#else + #define NO_DH +#endif + +/* AES */ +#if defined(WOLF_CONF_AESGCM) && WOLF_CONF_AESGCM == 1 + #define HAVE_AESGCM + /* GCM Method: GCM_SMALL, GCM_WORD32, GCM_TABLE or GCM_TABLE_4BIT */ + /* GCM_TABLE is about 4K larger and 3x faster for GHASH */ + #define GCM_SMALL + #define HAVE_AES_DECRYPT +#endif + +#if defined(WOLF_CONF_AESCBC) && WOLF_CONF_AESCBC == 1 + #define HAVE_AES_CBC + #define HAVE_AES_DECRYPT +#endif + +/* Other possible AES modes */ +//#define WOLFSSL_AES_COUNTER +//#define HAVE_AESCCM +//#define WOLFSSL_AES_XTS +//#define WOLFSSL_AES_DIRECT +//#define HAVE_AES_ECB +//#define HAVE_AES_KEYWRAP +//#define AES_MAX_KEY_SIZE 256 + +/* ChaCha20 / Poly1305 */ +#undef HAVE_CHACHA +#undef HAVE_POLY1305 +#if defined(WOLF_CONF_CHAPOLY) && WOLF_CONF_CHAPOLY == 1 + #define HAVE_CHACHA + #define HAVE_POLY1305 + + /* Needed for Poly1305 */ + #undef HAVE_ONE_TIME_AUTH + #define HAVE_ONE_TIME_AUTH +#endif + +/* Ed25519 / Curve25519 */ +#undef HAVE_CURVE25519 +#undef HAVE_ED25519 +#if defined(WOLF_CONF_EDCURVE25519) && WOLF_CONF_EDCURVE25519 == 1 + #define HAVE_CURVE25519 + #define HAVE_ED25519 + + /* Optionally use small math (less flash usage, but much slower) */ + #define CURVED25519_SMALL +#endif + +/* ------------------------------------------------------------------------- */ +/* Hashing */ +/* ------------------------------------------------------------------------- */ +/* Sha1 */ +#undef NO_SHA +#if defined(WOLF_CONF_SHA1) && WOLF_CONF_SHA1 == 1 + /* 1k smaller, but 25% slower */ + //#define USE_SLOW_SHA +#else + #define NO_SHA +#endif + +/* Sha2-256 */ +#undef NO_SHA256 +#if defined(WOLF_CONF_SHA2_256) && WOLF_CONF_SHA2_256 == 1 + /* not unrolled - ~2k smaller and ~25% slower */ + //#define USE_SLOW_SHA256 + + //#define WOLFSSL_SHAKE256 + + /* Sha2-224 */ + #if defined(WOLF_CONF_SHA2_224) && WOLF_CONF_SHA2_224 == 1 + #define WOLFSSL_SHA224 + #endif +#else + #define NO_SHA256 +#endif + +/* Sha2-512 */ +#undef WOLFSSL_SHA512 +#if defined(WOLF_CONF_SHA2_512) && WOLF_CONF_SHA2_512 == 1 + /* over twice as small, but 50% slower */ + //#define USE_SLOW_SHA512 + + #define WOLFSSL_SHA512 + #define HAVE_SHA512 /* freeRTOS settings.h requires this */ +#endif + +/* Sha2-384 */ +#undef WOLFSSL_SHA384 +#if defined(WOLF_CONF_SHA2_384) && WOLF_CONF_SHA2_384 == 1 + #define WOLFSSL_SHA384 +#endif + +/* Sha3 */ +#undef WOLFSSL_SHA3 +#if defined(WOLF_CONF_SHA3) && WOLF_CONF_SHA3 == 1 + #define WOLFSSL_SHA3 +#endif + +/* MD5 */ +#if defined(WOLF_CONF_MD5) && WOLF_CONF_MD5 == 1 + /* enabled */ +#else + #define NO_MD5 +#endif + +/* ------------------------------------------------------------------------- */ +/* Benchmark / Test */ +/* ------------------------------------------------------------------------- */ +/* Use reduced benchmark / test sizes */ +#define BENCH_EMBEDDED +#define USE_CERT_BUFFERS_2048 +#define USE_CERT_BUFFERS_256 + +/* ------------------------------------------------------------------------- */ +/* Debugging */ +/* ------------------------------------------------------------------------- */ +#if defined(WOLF_CONF_DEBUG) && WOLF_CONF_DEBUG == 1 + #define DEBUG_WOLFSSL + + /* Use this to measure / print heap usage */ + #if 0 + #define USE_WOLFSSL_MEMORY + #define WOLFSSL_TRACK_MEMORY + #define WOLFSSL_DEBUG_MEMORY + #define WOLFSSL_DEBUG_MEMORY_PRINT + #endif +#else + //#define NO_WOLFSSL_MEMORY + //#define NO_ERROR_STRINGS +#endif + +/* ------------------------------------------------------------------------- */ +/* Port */ +/* ------------------------------------------------------------------------- */ + +/* Override Current Time */ +/* Allows custom "custom_time()" function to be used for benchmark */ +#define WOLFSSL_USER_CURRTIME + +/* ------------------------------------------------------------------------- */ +/* RNG */ +/* ------------------------------------------------------------------------- */ +#define NO_OLD_RNGNAME /* conflicts with STM RNG macro */ +#if !defined(WOLF_CONF_RNG) || WOLF_CONF_RNG == 1 + /* default is enabled */ + #define HAVE_HASHDRBG +#else /* WOLF_CONF_RNG == 0 */ + #define WC_NO_HASHDRBG + #define WC_NO_RNG +#endif + +/* ------------------------------------------------------------------------- */ +/* Disable Features */ +/* ------------------------------------------------------------------------- */ +#if defined(WOLF_CONF_TLS12) && WOLF_CONF_TLS12 == 0 + #define WOLFSSL_NO_TLS12 +#endif +#if defined(WOLF_CONF_WOLFCRYPT_ONLY) && WOLF_CONF_WOLFCRYPT_ONLY == 1 + #define WOLFCRYPT_ONLY +#endif +//#define NO_WOLFSSL_SERVER +//#define NO_WOLFSSL_CLIENT + +#if defined(WOLF_CONF_TEST) && WOLF_CONF_TEST == 0 + #define NO_CRYPT_TEST + #define NO_CRYPT_BENCHMARK +#endif + +#define NO_FILESYSTEM +#define NO_WRITEV +#define NO_MAIN_DRIVER +#define NO_DEV_RANDOM +#define NO_OLD_TLS +#define WOLFSSL_NO_CLIENT_AUTH /* disable client auth for Ed25519/Ed448 */ + +#define NO_DSA +#define NO_RC4 +#define NO_MD4 +#define NO_DES3 + +/* In-lining of misc.c functions */ +/* If defined, must include wolfcrypt/src/misc.c in build */ +/* Slower, but about 1k smaller */ +//#define NO_INLINE + +/* Base16 / Base64 encoding */ +//#define NO_CODING + +/* bypass certificate date checking, due to lack of properly configured RTC source */ +#ifndef HAL_RTC_MODULE_ENABLED + #define NO_ASN_TIME +#endif + +#ifdef __cplusplus +} +#endif +#endif /* WOLFSSL_I_CUBE_WOLFSSL_CONF_H_H */ + +/** + * @} + */ + +/*****END OF FILE****/ diff --git a/STM32G0_Nucleo/Core/Src/main.c b/STM32G0_Nucleo/Core/Src/main.c new file mode 100644 index 0000000..8758e7c --- /dev/null +++ b/STM32G0_Nucleo/Core/Src/main.c @@ -0,0 +1,296 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include +#include + +#ifndef WOLFSSL_USER_SETTINGS + #include +#endif + +#include // For wc_PBKDF2_HMAC +#include // For wc_AesSetKeyDirect +#include +#include +#include +#include +#include +#include + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_IWDG_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +#define AES_BLOCK_SIZE 16 +#define KEY_SIZE 32 + +void encrypt_string(const char* password, int pLen, const char* salt, int sLen, int iteration_count, const char* plaintext, int ptLen) +{ + byte key[KEY_SIZE]; // 256-bit key + byte iv[AES_BLOCK_SIZE] = {0}; // Initialization Vector + byte ciphertext[1024]; // Adjust size as needed + int ciphertext_len; + + // Derive key from password and salt using PBKDF2-HMAC-SHA1 + if (wc_PBKDF2(key, (const byte*)password, pLen, (const byte*)salt, sLen, iteration_count, KEY_SIZE, WC_HASH_TYPE_SHA256) != 0) { + printf("Error deriving key\n"); + return; + } + + Aes aes; + if (wc_AesSetKey(&aes, key, KEY_SIZE, iv, AES_ENCRYPTION) != 0) { + printf("Error setting AES key\n"); + return; + } + + // Perform encryption + if (wc_AesCbcEncrypt(&aes, ciphertext, (const byte*)plaintext, ptLen) != 0) { + printf("Error encrypting data\n"); + return; + } + + // Clear the key from memory + memset(key, 0, sizeof(key)); + + // Print encrypted data as hex + printf("Encrypted (hex): "); + for (int i = 0; i < ptLen; i++) { + printf("%02x", ciphertext[i]); + } + printf("\n"); + + wc_AesFree(&aes); +} +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + // int ciphertext_len; + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_IWDG_Init(); + /* USER CODE BEGIN 2 */ + + wolfCrypt_Init(); + + char* password = "tecsantoshkumar_secret_key"; + char* salt = "tecsantoshkumarsalt_1"; + char* plaintext = "tecsantoshkumar"; + int iteration_count = 65536; + + byte key[KEY_SIZE]; // 256-bit key + byte iv[AES_BLOCK_SIZE] = {0}; // Initialization Vector + byte ciphertext[1024]; // Adjust size as needed + + + int rst = wc_PBKDF2(key, (byte*)password, strlen(password), (byte*)salt, strlen(salt), iteration_count, KEY_SIZE, WC_HASH_TYPE_SHA256); + + if (rst != 0) + { + printf("Error deriving key\n"); + } + encrypt_string(password, strlen(password), salt, strlen(salt), iteration_count, plaintext, strlen(plaintext)); + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief IWDG Initialization Function + * @param None + * @retval None + */ +static void MX_IWDG_Init(void) +{ + + /* USER CODE BEGIN IWDG_Init 0 */ + + /* USER CODE END IWDG_Init 0 */ + + /* USER CODE BEGIN IWDG_Init 1 */ + + /* USER CODE END IWDG_Init 1 */ + LL_IWDG_Enable(IWDG); + LL_IWDG_EnableWriteAccess(IWDG); + LL_IWDG_SetPrescaler(IWDG, LL_IWDG_PRESCALER_4); + LL_IWDG_SetReloadCounter(IWDG, 4095); + while (LL_IWDG_IsReady(IWDG) != 1) + { + } + + LL_IWDG_ReloadCounter(IWDG); + /* USER CODE BEGIN IWDG_Init 2 */ + + /* USER CODE END IWDG_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOA_CLK_ENABLE(); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/STM32G0_Nucleo/Core/Src/stm32g0xx_hal_msp.c b/STM32G0_Nucleo/Core/Src/stm32g0xx_hal_msp.c new file mode 100644 index 0000000..d488007 --- /dev/null +++ b/STM32G0_Nucleo/Core/Src/stm32g0xx_hal_msp.c @@ -0,0 +1,86 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g0xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral + */ + HAL_SYSCFG_StrobeDBattpinsConfig(SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE); + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + diff --git a/STM32G0_Nucleo/Core/Src/stm32g0xx_it.c b/STM32G0_Nucleo/Core/Src/stm32g0xx_it.c new file mode 100644 index 0000000..a676c7c --- /dev/null +++ b/STM32G0_Nucleo/Core/Src/stm32g0xx_it.c @@ -0,0 +1,146 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g0xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32g0xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M0+ Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVC_IRQn 0 */ + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32G0xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32g0xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + diff --git a/STM32G0_Nucleo/Core/Src/syscalls.c b/STM32G0_Nucleo/Core/Src/syscalls.c new file mode 100644 index 0000000..d190edf --- /dev/null +++ b/STM32G0_Nucleo/Core/Src/syscalls.c @@ -0,0 +1,176 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeIDE + * @brief STM32CubeIDE Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + (void)file; + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _open(char *path, int flags, ...) +{ + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + (void)status; + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + (void)name; + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + (void)buf; + return -1; +} + +int _stat(char *file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + (void)old; + (void)new; + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; +} diff --git a/STM32G0_Nucleo/Core/Src/sysmem.c b/STM32G0_Nucleo/Core/Src/sysmem.c new file mode 100644 index 0000000..921ecef --- /dev/null +++ b/STM32G0_Nucleo/Core/Src/sysmem.c @@ -0,0 +1,79 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeIDE + * @brief STM32CubeIDE System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the newlib libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} diff --git a/STM32G0_Nucleo/Core/Src/system_stm32g0xx.c b/STM32G0_Nucleo/Core/Src/system_stm32g0xx.c new file mode 100644 index 0000000..f142e1a --- /dev/null +++ b/STM32G0_Nucleo/Core/Src/system_stm32g0xx.c @@ -0,0 +1,302 @@ +/** + ****************************************************************************** + * @file system_stm32g0xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32g0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (8 MHz then 16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32g0xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB Prescaler | 1 + *----------------------------------------------------------------------------- + * HSI Division factor | 1 + *----------------------------------------------------------------------------- + * PLL_M | 1 + *----------------------------------------------------------------------------- + * PLL_N | 8 + *----------------------------------------------------------------------------- + * PLL_P | 7 + *----------------------------------------------------------------------------- + * PLL_Q | 2 + *----------------------------------------------------------------------------- + * PLL_R | 2 + *----------------------------------------------------------------------------- + * Require 48MHz for RNG | Disabled + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32g0xx_system + * @{ + */ + +/** @addtogroup STM32G0xx_System_Private_Includes + * @{ + */ + +#include "stm32g0xx.h" + +#if !defined (HSE_VALUE) +#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/ +#endif /* LSI_VALUE */ + +#if !defined (LSE_VALUE) + #define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/ +#endif /* LSE_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000UL; + + const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL}; + const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL}; + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE + * + * - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (**) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp; + uint32_t pllvco; + uint32_t pllr; + uint32_t pllsource; + uint32_t pllm; + uint32_t hsidiv; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_0: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + + case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */ + SystemCoreClock = LSI_VALUE; + break; + + case RCC_CFGR_SWS_2: /* LSE used as system clock */ + SystemCoreClock = LSE_VALUE; + break; + + case RCC_CFGR_SWS_1: /* PLL used as system clock */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL; + + if(pllsource == 0x03UL) /* HSE used as PLL clock source */ + { + pllvco = (HSE_VALUE / pllm); + } + else /* HSI used as PLL clock source */ + { + pllvco = (HSI_VALUE / pllm); + } + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL); + + SystemCoreClock = pllvco/pllr; + break; + + case 0x00000000U: /* HSI used as system clock */ + default: /* HSI used as system clock */ + hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos)); + SystemCoreClock = (HSI_VALUE/hsidiv); + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/STM32G0_Nucleo/Core/Startup/startup_stm32g0b1cbtx.s b/STM32G0_Nucleo/Core/Startup/startup_stm32g0b1cbtx.s new file mode 100644 index 0000000..8ed6cbc --- /dev/null +++ b/STM32G0_Nucleo/Core/Startup/startup_stm32g0b1cbtx.s @@ -0,0 +1,295 @@ +/** + ****************************************************************************** + * @file startup_stm32g0b1xx.s + * @author MCD Application Team + * @brief STM32G0b1xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0+ processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application s entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_VDDIO2_IRQHandler /* PVD through EXTI Line detect */ + .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_CRS_IRQHandler /* RCC & CRS */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word USB_UCPD1_2_IRQHandler /* USB, UCPD1, UCPD2 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler /* DMA1 Ch4 to Ch7, DMA2 Ch1 to Ch5, DMAMUX1 overrun */ + .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_TIM4_IRQHandler /* TIM3, TIM4 */ + .word TIM6_DAC_LPTIM1_IRQHandler /* TIM6, DAC and LPTIM1 */ + .word TIM7_LPTIM2_IRQHandler /* TIM7 and LPTIM2 */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_FDCAN_IT0_IRQHandler /* TIM16 & FDCAN1_IT0 & FDCAN2_IT0 */ + .word TIM17_FDCAN_IT1_IRQHandler /* TIM17 & FDCAN1_IT1 & FDCAN2_IT1 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_3_IRQHandler /* I2C2, I2C3 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_3_IRQHandler /* SPI2, SPI3 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_LPUART2_IRQHandler /* USART2 & LPUART2 */ + .word USART3_4_5_6_LPUART1_IRQHandler /* USART3, USART4, USART5, USART6, LPUART1 */ + .word CEC_IRQHandler /* CEC */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_VDDIO2_IRQHandler + .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler + + .weak RTC_TAMP_IRQHandler + .thumb_set RTC_TAMP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_CRS_IRQHandler + .thumb_set RCC_CRS_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak USB_UCPD1_2_IRQHandler + .thumb_set USB_UCPD1_2_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler + .thumb_set DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak ADC1_COMP_IRQHandler + .thumb_set ADC1_COMP_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_TIM4_IRQHandler + .thumb_set TIM3_TIM4_IRQHandler,Default_Handler + + .weak TIM6_DAC_LPTIM1_IRQHandler + .thumb_set TIM6_DAC_LPTIM1_IRQHandler,Default_Handler + + .weak TIM7_LPTIM2_IRQHandler + .thumb_set TIM7_LPTIM2_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_FDCAN_IT0_IRQHandler + .thumb_set TIM16_FDCAN_IT0_IRQHandler,Default_Handler + + .weak TIM17_FDCAN_IT1_IRQHandler + .thumb_set TIM17_FDCAN_IT1_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_3_IRQHandler + .thumb_set I2C2_3_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_3_IRQHandler + .thumb_set SPI2_3_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_LPUART2_IRQHandler + .thumb_set USART2_LPUART2_IRQHandler,Default_Handler + + .weak USART3_4_5_6_LPUART1_IRQHandler + .thumb_set USART3_4_5_6_LPUART1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler diff --git a/STM32G0_Nucleo/walfssl.ioc b/STM32G0_Nucleo/walfssl.ioc new file mode 100644 index 0000000..90e9137 --- /dev/null +++ b/STM32G0_Nucleo/walfssl.ioc @@ -0,0 +1,142 @@ +#MicroXplorer Configuration settings - do not modify +CAD.formats= +CAD.pinconfig= +CAD.provider= +File.Version=6 +GPIO.groupedBy= +KeepUserPlacement=false +Mcu.CPN=STM32G0B1CBT3 +Mcu.Family=STM32G0 +Mcu.IP0=IWDG +Mcu.IP1=NVIC +Mcu.IP2=RCC +Mcu.IP3=SYS +Mcu.IPNb=4 +Mcu.Name=STM32G0B1C(B-C-E)Tx +Mcu.Package=LQFP48 +Mcu.Pin0=PA13 +Mcu.Pin1=PA14-BOOT0 +Mcu.Pin2=VP_IWDG_VS_IWDG +Mcu.Pin3=VP_SYS_VS_Systick +Mcu.Pin4=VP_SYS_VS_DBSignals +Mcu.Pin5=VP_wolfSSL.I-CUBE-wolfSSL_VS_wolfSSLJjwolfSSL_5.5.4_5.5.4 +Mcu.PinsNb=6 +Mcu.ThirdParty0=wolfSSL.I-CUBE-wolfSSL.5.5.4 +Mcu.ThirdPartyNb=1 +Mcu.UserConstants= +Mcu.UserName=STM32G0B1CBTx +MxCube.Version=6.4.0 +MxDb.Version=DB.6.0.40 +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true +NVIC.SysTick_IRQn=true\:3\:0\:false\:false\:true\:false\:true\:false +PA13.Mode=Serial_Wire +PA13.Signal=SYS_SWDIO +PA14-BOOT0.Locked=true +PA14-BOOT0.Mode=Serial_Wire +PA14-BOOT0.Signal=SYS_SWCLK +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32G0B1CBTx +ProjectManager.FirmwarePackage=STM32Cube FW_G0 V1.5.1 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain=STM32CubeIDE +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=walfssl.ioc +ProjectManager.ProjectName=walfssl +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=STM32CubeIDE +ProjectManager.ToolChainLocation= +ProjectManager.UAScriptAfterPath= +ProjectManager.UAScriptBeforePath= +ProjectManager.UnderRoot=true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_IWDG_Init-IWDG-false-LL-true +RCC.AHBFreq_Value=16000000 +RCC.APBFreq_Value=16000000 +RCC.APBTimFreq_Value=16000000 +RCC.CECFreq_Value=32786.88524590164 +RCC.CortexFreq_Value=16000000 +RCC.EXTERNAL_CLOCK_VALUE=48000 +RCC.FCLKCortexFreq_Value=16000000 +RCC.FDCANCLockSelection=RCC_FDCANCLKSOURCE_PLL +RCC.FDCANFreq_Value=64000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=16000000 +RCC.HSE_VALUE=8000000 +RCC.HSI48_VALUE=48000000 +RCC.HSI_VALUE=16000000 +RCC.I2C1Freq_Value=16000000 +RCC.I2C2Freq_Value=16000000 +RCC.I2S1Freq_Value=16000000 +RCC.I2S2Freq_Value=16000000 +RCC.IPParameters=AHBFreq_Value,APBFreq_Value,APBTimFreq_Value,CECFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANCLockSelection,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2S1Freq_Value,I2S2Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LPUART2Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,SYSCLKFreq_VALUE,TIM15Freq_Value,TIM1Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value +RCC.LPTIM1Freq_Value=16000000 +RCC.LPTIM2Freq_Value=16000000 +RCC.LPUART1Freq_Value=16000000 +RCC.LPUART2Freq_Value=16000000 +RCC.LSCOPinFreq_Value=32000 +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.MCO1PinFreq_Value=16000000 +RCC.MCO2PinFreq_Value=16000000 +RCC.PLLPoutputFreq_Value=64000000 +RCC.PLLQoutputFreq_Value=64000000 +RCC.PLLRCLKFreq_Value=64000000 +RCC.PWRFreq_Value=16000000 +RCC.SYSCLKFreq_VALUE=16000000 +RCC.TIM15Freq_Value=16000000 +RCC.TIM1Freq_Value=16000000 +RCC.USART1Freq_Value=16000000 +RCC.USART2Freq_Value=16000000 +RCC.USART3Freq_Value=16000000 +RCC.USBFreq_Value=48000000 +RCC.VCOInputFreq_Value=16000000 +RCC.VCOOutputFreq_Value=128000000 +VP_IWDG_VS_IWDG.Mode=IWDG_Activate +VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG +VP_SYS_VS_DBSignals.Mode=DisableDeadBatterySignals +VP_SYS_VS_DBSignals.Signal=SYS_VS_DBSignals +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_wolfSSL.I-CUBE-wolfSSL_VS_wolfSSLJjwolfSSL_5.5.4_5.5.4.Mode=wolfSSLJjwolfSSL +VP_wolfSSL.I-CUBE-wolfSSL_VS_wolfSSLJjwolfSSL_5.5.4_5.5.4.Signal=wolfSSL.I-CUBE-wolfSSL_VS_wolfSSLJjwolfSSL_5.5.4_5.5.4 +board=custom +wolfSSL.I-CUBE-wolfSSL.5.5.4.IPParameters=WOLF_CONF_DEBUG,WOLF_CONF_WOLFCRYPT_ONLY,WOLF_CONF_AESCBC,WOLF_CONF_AESGCM,WOLF_CONF_MD5,WOLF_CONF_PSK,WOLF_CONF_PWDBASED,WOLF_CONF_KEEP_PEER_CERT,WOLF_CONF_BASE64_ENCODE,WOLF_CONF_OPENSSL_EXTRA,WOLF_CONF_RNG,WOLF_CONF_RSA,WOLF_CONF_ECC,WOLF_CONF_DH,wolfSSLCcwolfSSLJjwolfSSLJjCore,wolfSSLCcwolfSSLJjwolfCryptJjCore,wolfSSLCcwolfSSLJjwolfCryptJjTest +wolfSSL.I-CUBE-wolfSSL.5.5.4.WOLF_CONF_AESCBC=1 +wolfSSL.I-CUBE-wolfSSL.5.5.4.WOLF_CONF_AESGCM=0 +wolfSSL.I-CUBE-wolfSSL.5.5.4.WOLF_CONF_BASE64_ENCODE=1 +wolfSSL.I-CUBE-wolfSSL.5.5.4.WOLF_CONF_DEBUG=1 +wolfSSL.I-CUBE-wolfSSL.5.5.4.WOLF_CONF_DH=0 +wolfSSL.I-CUBE-wolfSSL.5.5.4.WOLF_CONF_ECC=0 +wolfSSL.I-CUBE-wolfSSL.5.5.4.WOLF_CONF_KEEP_PEER_CERT=1 +wolfSSL.I-CUBE-wolfSSL.5.5.4.WOLF_CONF_MD5=1 +wolfSSL.I-CUBE-wolfSSL.5.5.4.WOLF_CONF_OPENSSL_EXTRA=2 +wolfSSL.I-CUBE-wolfSSL.5.5.4.WOLF_CONF_PSK=1 +wolfSSL.I-CUBE-wolfSSL.5.5.4.WOLF_CONF_PWDBASED=1 +wolfSSL.I-CUBE-wolfSSL.5.5.4.WOLF_CONF_RNG=0 +wolfSSL.I-CUBE-wolfSSL.5.5.4.WOLF_CONF_RSA=0 +wolfSSL.I-CUBE-wolfSSL.5.5.4.WOLF_CONF_WOLFCRYPT_ONLY=1 +wolfSSL.I-CUBE-wolfSSL.5.5.4.wolfSSLCcwolfSSLJjwolfCryptJjCore=true +wolfSSL.I-CUBE-wolfSSL.5.5.4.wolfSSLCcwolfSSLJjwolfCryptJjTest=true +wolfSSL.I-CUBE-wolfSSL.5.5.4.wolfSSLCcwolfSSLJjwolfSSLJjCore=true +wolfSSL.I-CUBE-wolfSSL.5.5.4.wolfSSLJjwolfSSL_Checked=true +wolfSSL.I-CUBE-wolfSSL.5.5.4_SwParameter=wolfSSLCcwolfSSLJjwolfCryptJjCore\:true;wolfSSLCcwolfSSLJjwolfCryptJjTest\:true;wolfSSLCcwolfSSLJjwolfSSLJjCore\:true;