@@ -4020,30 +4020,37 @@ static int dilithium_expand_s(wc_Shake* shake256, byte* priv_seed, byte eta,
40204020 int ret = 0 ;
40214021
40224022#if defined(USE_INTEL_SPEEDUP ) && !defined(WC_SHA3_NO_ASM )
4023- if (IS_INTEL_AVX2 (cpuid_flags ) && (SAVE_VECTOR_REGISTERS2 () == 0 )) {
4024-
40254023 #ifndef WOLFSSL_NO_ML_DSA_44
4026- if (s1Len == 4 ) {
4027- sword32 * s [2 ] = { s1 , s2 };
4028- ret = wc_mldsa_gen_s_4_4_avx2 (s , priv_seed );
4029- }
4024+ if ((s1Len == 4 ) && IS_INTEL_AVX2 (cpuid_flags ) &&
4025+ (SAVE_VECTOR_REGISTERS2 () == 0 ))
4026+ {
4027+ sword32 * s [2 ] = { s1 , s2 };
4028+ ret = wc_mldsa_gen_s_4_4_avx2 (s , priv_seed );
4029+ RESTORE_VECTOR_REGISTERS ();
4030+ }
4031+ else
40304032 #endif
40314033 #ifndef WOLFSSL_NO_ML_DSA_65
4032- if (s1Len == 5 ) {
4033- sword32 * s [2 ] = { s1 , s2 };
4034- ret = wc_mldsa_gen_s_5_6_avx2 (s , priv_seed );
4035- }
4034+ if ((s1Len == 5 ) && IS_INTEL_AVX2 (cpuid_flags ) &&
4035+ (SAVE_VECTOR_REGISTERS2 () == 0 ))
4036+ {
4037+ sword32 * s [2 ] = { s1 , s2 };
4038+ ret = wc_mldsa_gen_s_5_6_avx2 (s , priv_seed );
4039+ RESTORE_VECTOR_REGISTERS ();
4040+ }
4041+ else
40364042 #endif
40374043 #ifndef WOLFSSL_NO_ML_DSA_87
4038- if (s1Len == 7 ) {
4039- sword32 * s [ 2 ] = { s1 , s2 };
4040- ret = wc_mldsa_gen_s_7_8_avx2 ( s , priv_seed );
4041- }
4042- #endif
4044+ if (( s1Len == 7 ) && IS_INTEL_AVX2 ( cpuid_flags ) &&
4045+ ( SAVE_VECTOR_REGISTERS2 () == 0 ))
4046+ {
4047+ sword32 * s [ 2 ] = { s1 , s2 };
4048+ ret = wc_mldsa_gen_s_7_8_avx2 ( s , priv_seed );
40434049 RESTORE_VECTOR_REGISTERS ();
40444050 }
40454051 else
4046- #endif
4052+ #endif
4053+ #endif /* USE_INTEL_SPEEDUP && !WC_SHA3_NO_ASM */
40474054 {
40484055 ret = dilithium_expand_s_c (shake256 , priv_seed , eta , s1 , s1Len , s2 ,
40494056 s2Len );
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