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Two captures of the actual electrical signal between pins 5 and 4. The jitter is noticeable, and is of the same general 9-21ms high time as was reported in code. Rise time is negligable. |
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Quick record of some write-to-read latency checkout I did. I wired the signal pins together on smartio ports 0/1, 2/3, and 4/5.
I ran the code in this testcase on alpha 4.
A quick screenshot of the results - looks like 10-20ms of delay, with some variation in that range.
Punchline: As of this release, from the time the pin is physically toggled to the time it's read in code could be between 10ms to 20ms.
Per some discord discussion, this is known to be longer than the RIO's io processing latency. I don't see an inherent problem here and I think there's some improvements, but just tossing the result out for a current snapshot.
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