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2279 lines (2097 loc) · 145 KB
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Release 14.7 - xst P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.02 secs
-->
Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.03 secs
-->
Reading design: Top.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "Top.prj"
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "Top"
Output Format : NGC
Target Device : xc7k160t-1-ffg676
---- Source Options
Top Module Name : Top
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Shift Register Extraction : YES
ROM Style : Auto
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : Auto
Automatic Register Balancing : No
---- Target Options
LUT Combining : Auto
Reduce Control Sets : Auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 32
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Parsing *
=========================================================================
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/SegmentDecoder.v" into library work
Parsing module <SegmentDecoder>.
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/ShiftReg.v" into library work
Parsing module <ShiftReg>.
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/Seg7Remap.v" into library work
Parsing module <Seg7Remap>.
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/Seg7Decode.v" into library work
Parsing module <Seg7Decode>.
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/PS2.v" into library work
Parsing module <PS2>.
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/pbdebounce.v" into library work
Parsing module <pbdebounce>.
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/AntiJitter.v" into library work
Parsing module <AntiJitter>.
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/vgac.v" into library work
Parsing module <vgac>.
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/speedup.v" into library work
Parsing module <speedup>.
WARNING:HDLCompiler:751 - "/home/wxxcl/ISE_workspace/DinoGame/speedup.v" Line 25: Redeclaration of ansi port speed is not allowed
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/Seg7Device.v" into library work
Parsing module <Seg7Device>.
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/night.v" into library work
Parsing module <night>.
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/Load_Gen.v" into library work
Parsing module <Load_Gen>.
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/Keypad.v" into library work
Parsing module <Keypad>.
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/Keyboard.v" into library work
Parsing module <Keyboard>.
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/ground.v" into library work
Parsing module <ground>.
WARNING:HDLCompiler:568 - "/home/wxxcl/ISE_workspace/DinoGame/ground.v" Line 43: Constant value is truncated to fit in <10> bits.
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/grade.v" into library work
Parsing module <grade>.
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/gameover.v" into library work
Parsing module <gameover>.
WARNING:HDLCompiler:751 - "/home/wxxcl/ISE_workspace/DinoGame/gameover.v" Line 31: Redeclaration of ansi port vga_data is not allowed
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/dinosaur.v" into library work
Parsing module <dinosaur>.
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/ctrl.v" into library work
Parsing module <ctrl>.
WARNING:HDLCompiler:751 - "/home/wxxcl/ISE_workspace/DinoGame/ctrl.v" Line 28: Redeclaration of ansi port show is not allowed
WARNING:HDLCompiler:751 - "/home/wxxcl/ISE_workspace/DinoGame/ctrl.v" Line 29: Redeclaration of ansi port jump is not allowed
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/cloud.v" into library work
Parsing module <cloud>.
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/bird_cactus.v" into library work
Parsing module <bird_cactus>.
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/beep.v" into library work
Parsing module <beep>.
Analyzing Verilog file "/home/wxxcl/ISE_workspace/DinoGame/Top.v" into library work
Parsing module <Top>.
=========================================================================
* HDL Elaboration *
=========================================================================
WARNING:HDLCompiler:1016 - "/home/wxxcl/ISE_workspace/DinoGame/Top.v" Line 59: Port dbg_keyLine is not connected to this instance
WARNING:HDLCompiler:1016 - "/home/wxxcl/ISE_workspace/DinoGame/Top.v" Line 63: Port segment is not connected to this instance
WARNING:HDLCompiler:1016 - "/home/wxxcl/ISE_workspace/DinoGame/Top.v" Line 98: Port rdn is not connected to this instance
Elaborating module <Top>.
Elaborating module <AntiJitter(WIDTH=4)>.
Elaborating module <Keypad>.
WARNING:HDLCompiler:1127 - "/home/wxxcl/ISE_workspace/DinoGame/Top.v" Line 59: Assignment to keyCode ignored, since the identifier is never used
Elaborating module <Seg7Device>.
Elaborating module <Seg7Decode>.
Elaborating module <SegmentDecoder>.
Elaborating module <Seg7Remap>.
Elaborating module <ShiftReg(WIDTH=64)>.
WARNING:HDLCompiler:1016 - "/home/wxxcl/ISE_workspace/DinoGame/Keyboard.v" Line 12: Port ready is not connected to this instance
Elaborating module <Keyboard>.
Elaborating module <PS2>.
Elaborating module <vgac>.
WARNING:HDLCompiler:604 - "/home/wxxcl/ISE_workspace/DinoGame/Top.v" Line 101: Module instantiation should have an instance name
Elaborating module <Load_Gen>.
Elaborating module <pbdebounce>.
Elaborating module <speedup>.
Elaborating module <ground>.
WARNING:HDLCompiler:413 - "/home/wxxcl/ISE_workspace/DinoGame/ground.v" Line 55: Result of 22-bit expression is truncated to fit in 21-bit target.
WARNING:HDLCompiler:413 - "/home/wxxcl/ISE_workspace/DinoGame/ground.v" Line 59: Result of 12-bit expression is truncated to fit in 11-bit target.
Elaborating module <cloud>.
WARNING:HDLCompiler:413 - "/home/wxxcl/ISE_workspace/DinoGame/cloud.v" Line 79: Result of 15-bit expression is truncated to fit in 10-bit target.
WARNING:HDLCompiler:413 - "/home/wxxcl/ISE_workspace/DinoGame/cloud.v" Line 85: Result of 11-bit expression is truncated to fit in 10-bit target.
WARNING:HDLCompiler:413 - "/home/wxxcl/ISE_workspace/DinoGame/cloud.v" Line 87: Result of 15-bit expression is truncated to fit in 10-bit target.
WARNING:HDLCompiler:413 - "/home/wxxcl/ISE_workspace/DinoGame/cloud.v" Line 103: Result of 15-bit expression is truncated to fit in 10-bit target.
WARNING:HDLCompiler:413 - "/home/wxxcl/ISE_workspace/DinoGame/cloud.v" Line 104: Result of 22-bit expression is truncated to fit in 21-bit target.
Elaborating module <dinosaur>.
WARNING:HDLCompiler:413 - "/home/wxxcl/ISE_workspace/DinoGame/dinosaur.v" Line 314: Result of 22-bit expression is truncated to fit in 21-bit target.
WARNING:HDLCompiler:413 - "/home/wxxcl/ISE_workspace/DinoGame/dinosaur.v" Line 338: Result of 32-bit expression is truncated to fit in 9-bit target.
WARNING:HDLCompiler:413 - "/home/wxxcl/ISE_workspace/DinoGame/dinosaur.v" Line 343: Result of 10-bit expression is truncated to fit in 9-bit target.
WARNING:HDLCompiler:1127 - "/home/wxxcl/ISE_workspace/DinoGame/dinosaur.v" Line 280: Assignment to cnt ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/wxxcl/ISE_workspace/DinoGame/Top.v" Line 105: Assignment to x ignored, since the identifier is never used
Elaborating module <bird_cactus>.
WARNING:HDLCompiler:413 - "/home/wxxcl/ISE_workspace/DinoGame/bird_cactus.v" Line 290: Result of 22-bit expression is truncated to fit in 21-bit target.
WARNING:HDLCompiler:413 - "/home/wxxcl/ISE_workspace/DinoGame/bird_cactus.v" Line 334: Result of 22-bit expression is truncated to fit in 21-bit target.
WARNING:HDLCompiler:413 - "/home/wxxcl/ISE_workspace/DinoGame/bird_cactus.v" Line 344: Result of 12-bit expression is truncated to fit in 10-bit target.
WARNING:HDLCompiler:413 - "/home/wxxcl/ISE_workspace/DinoGame/bird_cactus.v" Line 345: Result of 15-bit expression is truncated to fit in 9-bit target.
WARNING:HDLCompiler:413 - "/home/wxxcl/ISE_workspace/DinoGame/bird_cactus.v" Line 350: Result of 12-bit expression is truncated to fit in 10-bit target.
WARNING:HDLCompiler:413 - "/home/wxxcl/ISE_workspace/DinoGame/bird_cactus.v" Line 351: Result of 15-bit expression is truncated to fit in 9-bit target.
Elaborating module <gameover>.
WARNING:HDLCompiler:189 - "/home/wxxcl/ISE_workspace/DinoGame/Top.v" Line 107: Size mismatch in connection of port <clkdiv>. Formal port size is 33-bit while actual signal size is 32-bit.
Elaborating module <night>.
Elaborating module <ctrl>.
Elaborating module <grade>.
Elaborating module <beep>.
WARNING:HDLCompiler:413 - "/home/wxxcl/ISE_workspace/DinoGame/beep.v" Line 11: Result of 26-bit expression is truncated to fit in 25-bit target.
Elaborating module <ShiftReg(WIDTH=16)>.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <Top>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/Top.v".
WARNING:Xst:647 - Input <rstn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/wxxcl/ISE_workspace/DinoGame/Top.v" line 59: Output port <keyCode> of the instance <k0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/wxxcl/ISE_workspace/DinoGame/Top.v" line 59: Output port <dbg_keyLine> of the instance <k0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/wxxcl/ISE_workspace/DinoGame/Top.v" line 59: Output port <ready> of the instance <k0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/wxxcl/ISE_workspace/DinoGame/Top.v" line 63: Output port <segment> of the instance <segDevice> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/wxxcl/ISE_workspace/DinoGame/Top.v" line 63: Output port <anode> of the instance <segDevice> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/wxxcl/ISE_workspace/DinoGame/Top.v" line 98: Output port <rdn> of the instance <v0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/wxxcl/ISE_workspace/DinoGame/Top.v" line 105: Output port <x> of the instance <dino> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/wxxcl/ISE_workspace/DinoGame/Top.v" line 105: Output port <y> of the instance <dino> is unconnected or connected to loadless signal.
Found 32-bit register for signal <clkdiv>.
Found 32-bit adder for signal <clkdiv[31]_GND_1_o_add_1_OUT> created at line 52.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 32 D-type flip-flop(s).
Unit <Top> synthesized.
Synthesizing Unit <AntiJitter>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/AntiJitter.v".
WIDTH = 4
Found 4-bit register for signal <cnt>.
Found 1-bit register for signal <O>.
Found 4-bit subtractor for signal <cnt[3]_GND_2_o_sub_6_OUT> created at line 39.
Found 4-bit adder for signal <cnt[3]_GND_2_o_add_2_OUT> created at line 34.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 5 D-type flip-flop(s).
Unit <AntiJitter> synthesized.
Synthesizing Unit <Keypad>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/Keypad.v".
Found 4-bit register for signal <keyLineX>.
Found 1-bit register for signal <state>.
Found 5-bit register for signal <keyLineY>.
Found 1-bit tristate buffer for signal <keyX<3>> created at line 29
Found 1-bit tristate buffer for signal <keyX<2>> created at line 29
Found 1-bit tristate buffer for signal <keyX<1>> created at line 29
Found 1-bit tristate buffer for signal <keyX<0>> created at line 29
Found 1-bit tristate buffer for signal <keyY<4>> created at line 30
Found 1-bit tristate buffer for signal <keyY<3>> created at line 30
Found 1-bit tristate buffer for signal <keyY<2>> created at line 30
Found 1-bit tristate buffer for signal <keyY<1>> created at line 30
Found 1-bit tristate buffer for signal <keyY<0>> created at line 30
Summary:
inferred 10 D-type flip-flop(s).
inferred 9 Tristate(s).
Unit <Keypad> synthesized.
Synthesizing Unit <Seg7Device>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/Seg7Device.v".
Found 4x4-bit Read Only RAM for signal <anode>
Found 8-bit 4-to-1 multiplexer for signal <segment> created at line 36.
Summary:
inferred 1 RAM(s).
inferred 1 Multiplexer(s).
Unit <Seg7Device> synthesized.
Synthesizing Unit <Seg7Decode>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/Seg7Decode.v".
Summary:
no macro.
Unit <Seg7Decode> synthesized.
Synthesizing Unit <SegmentDecoder>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/SegmentDecoder.v".
Found 16x7-bit Read Only RAM for signal <segment>
Summary:
inferred 1 RAM(s).
Unit <SegmentDecoder> synthesized.
Synthesizing Unit <Seg7Remap>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/Seg7Remap.v".
Summary:
no macro.
Unit <Seg7Remap> synthesized.
Synthesizing Unit <ShiftReg_1>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/ShiftReg.v".
WIDTH = 64
DELAY = 12
Found 1-bit register for signal <oe>.
Found 12-bit register for signal <counter>.
Found 65-bit register for signal <shift>.
Found 12-bit adder for signal <counter[11]_GND_17_o_add_5_OUT> created at line 54.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 78 D-type flip-flop(s).
inferred 1 Multiplexer(s).
Unit <ShiftReg_1> synthesized.
Synthesizing Unit <Keyboard>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/Keyboard.v".
INFO:Xst:3210 - "/home/wxxcl/ISE_workspace/DinoGame/Keyboard.v" line 12: Output port <ready> of the instance <m0> is unconnected or connected to loadless signal.
Found 3-bit register for signal <state>.
Summary:
inferred 3 D-type flip-flop(s).
Unit <Keyboard> synthesized.
Synthesizing Unit <PS2>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/PS2.v".
Found 1-bit register for signal <ps2_clk_flag1>.
Found 1-bit register for signal <ps2_clk_flag2>.
Found 4-bit register for signal <num>.
Found 1-bit register for signal <negedge_ps2_clk_shift>.
Found 8-bit register for signal <temp_data>.
Found 1-bit register for signal <data_break>.
Found 10-bit register for signal <data>.
Found 1-bit register for signal <data_done>.
Found 1-bit register for signal <data_expand>.
Found 1-bit register for signal <ps2_clk_flag0>.
Found 4-bit adder for signal <num[3]_GND_19_o_add_1_OUT> created at line 56.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 29 D-type flip-flop(s).
Unit <PS2> synthesized.
Synthesizing Unit <vgac>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/vgac.v".
Found 10-bit register for signal <v_count>.
Found 9-bit register for signal <row_addr>.
Found 10-bit register for signal <col_addr>.
Found 1-bit register for signal <rdn>.
Found 1-bit register for signal <hs>.
Found 1-bit register for signal <vs>.
Found 4-bit register for signal <r>.
Found 4-bit register for signal <g>.
Found 4-bit register for signal <b>.
Found 10-bit register for signal <h_count>.
Found 10-bit subtractor for signal <col> created at line 69.
Found 10-bit adder for signal <h_count[9]_GND_20_o_add_2_OUT> created at line 44.
Found 10-bit adder for signal <v_count[9]_GND_20_o_add_8_OUT> created at line 63.
Found 9-bit subtractor for signal <row<8:0>> created at line 68.
Found 10-bit comparator greater for signal <h_sync> created at line 70
Found 10-bit comparator greater for signal <v_sync> created at line 71
Found 10-bit comparator greater for signal <GND_20_o_h_count[9]_LessThan_17_o> created at line 72
Found 10-bit comparator greater for signal <h_count[9]_PWR_12_o_LessThan_18_o> created at line 73
Found 10-bit comparator greater for signal <GND_20_o_v_count[9]_LessThan_19_o> created at line 74
Found 10-bit comparator greater for signal <v_count[9]_PWR_12_o_LessThan_20_o> created at line 75
Summary:
inferred 4 Adder/Subtractor(s).
inferred 54 D-type flip-flop(s).
inferred 6 Comparator(s).
inferred 1 Multiplexer(s).
Unit <vgac> synthesized.
Synthesizing Unit <Load_Gen>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/Load_Gen.v".
Found 1-bit register for signal <old_btn>.
Found 1-bit register for signal <Load_out>.
Summary:
inferred 2 D-type flip-flop(s).
Unit <Load_Gen> synthesized.
Synthesizing Unit <pbdebounce>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/pbdebounce.v".
Found 1-bit register for signal <pbreg>.
Found 7-bit register for signal <pbshift<6:0>>.
Summary:
inferred 8 D-type flip-flop(s).
Unit <pbdebounce> synthesized.
Synthesizing Unit <speedup>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/speedup.v".
Found 21-bit register for signal <speed>.
Found 32-bit register for signal <count>.
Found 21-bit subtractor for signal <speed[20]_GND_23_o_sub_5_OUT> created at line 37.
Found 32-bit adder for signal <count[31]_GND_23_o_add_1_OUT> created at line 29.
Found 32-bit comparator greater for signal <GND_23_o_count[31]_LessThan_4_o> created at line 34
Summary:
inferred 2 Adder/Subtractor(s).
inferred 53 D-type flip-flop(s).
inferred 1 Comparator(s).
Unit <speedup> synthesized.
Synthesizing Unit <ground>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/ground.v".
y0 = 9'b100110111
WARNING:Xst:2999 - Signal 'rom_data', unconnected in block 'ground', is tied to its initial value.
Found 11-bit register for signal <bais>.
Found 21-bit register for signal <cnt>.
Found 1-bit register for signal <_vga_data>.
Found 9-bit subtractor for signal <y> created at line 42.
Found 11-bit adder for signal <GND_24_o_bais[10]_add_1_OUT> created at line 43.
Found 21-bit adder for signal <cnt[20]_GND_24_o_add_4_OUT> created at line 55.
Found 11-bit adder for signal <bais[10]_GND_24_o_add_8_OUT> created at line 59.
Found 65536x1-bit Read Only RAM for signal <y[4]_read_port_6_OUT<0>>
Found 9-bit comparator lessequal for signal <y[8]_GND_24_o_LessThan_6_o> created at line 56
Found 21-bit comparator equal for signal <cnt[20]_speed[20]_equal_8_o> created at line 57
Summary:
inferred 1 RAM(s).
inferred 4 Adder/Subtractor(s).
inferred 33 D-type flip-flop(s).
inferred 2 Comparator(s).
inferred 1 Multiplexer(s).
Unit <ground> synthesized.
Synthesizing Unit <mod_11u_10u>.
Related source file is "".
Found 21-bit adder for signal <GND_25_o_b[9]_add_1_OUT> created at line 0.
Found 20-bit adder for signal <GND_25_o_b[9]_add_3_OUT> created at line 0.
Found 19-bit adder for signal <GND_25_o_b[9]_add_5_OUT> created at line 0.
Found 18-bit adder for signal <GND_25_o_b[9]_add_7_OUT> created at line 0.
Found 17-bit adder for signal <GND_25_o_b[9]_add_9_OUT> created at line 0.
Found 16-bit adder for signal <GND_25_o_b[9]_add_11_OUT> created at line 0.
Found 15-bit adder for signal <GND_25_o_b[9]_add_13_OUT> created at line 0.
Found 14-bit adder for signal <GND_25_o_b[9]_add_15_OUT> created at line 0.
Found 13-bit adder for signal <GND_25_o_b[9]_add_17_OUT> created at line 0.
Found 12-bit adder for signal <GND_25_o_b[9]_add_19_OUT> created at line 0.
Found 11-bit adder for signal <a[10]_b[9]_add_21_OUT> created at line 0.
Found 11-bit adder for signal <a[10]_GND_25_o_add_23_OUT> created at line 0.
Found 21-bit comparator lessequal for signal <BUS_0001> created at line 0
Found 20-bit comparator lessequal for signal <BUS_0002> created at line 0
Found 19-bit comparator lessequal for signal <BUS_0003> created at line 0
Found 18-bit comparator lessequal for signal <BUS_0004> created at line 0
Found 17-bit comparator lessequal for signal <BUS_0005> created at line 0
Found 16-bit comparator lessequal for signal <BUS_0006> created at line 0
Found 15-bit comparator lessequal for signal <BUS_0007> created at line 0
Found 14-bit comparator lessequal for signal <BUS_0008> created at line 0
Found 13-bit comparator lessequal for signal <BUS_0009> created at line 0
Found 12-bit comparator lessequal for signal <BUS_0010> created at line 0
Found 11-bit comparator lessequal for signal <BUS_0011> created at line 0
Found 11-bit comparator lessequal for signal <BUS_0012> created at line 0
Summary:
inferred 12 Adder/Subtractor(s).
inferred 12 Comparator(s).
inferred 122 Multiplexer(s).
Unit <mod_11u_10u> synthesized.
Synthesizing Unit <cloud>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/cloud.v".
color = 12'b110111011101
width = 78
height = 24
WARNING:Xst:2999 - Signal 'rom_data', unconnected in block 'cloud', is tied to its initial value.
Found 1-bit register for signal <x<1><6>>.
Found 1-bit register for signal <x<1><8>>.
Found 21-bit register for signal <cnt>.
Found 1-bit register for signal <en<1>>.
Found 1-bit register for signal <x<0><9>>.
Found 1-bit register for signal <x<0><8>>.
Found 1-bit register for signal <x<0><7>>.
Found 1-bit register for signal <x<0><6>>.
Found 1-bit register for signal <x<0><5>>.
Found 1-bit register for signal <x<0><4>>.
Found 1-bit register for signal <x<0><3>>.
Found 1-bit register for signal <x<0><2>>.
Found 1-bit register for signal <x<0><1>>.
Found 1-bit register for signal <x<0><0>>.
Found 1-bit register for signal <x<1><9>>.
Found 1-bit register for signal <x<1><7>>.
Found 1-bit register for signal <x<1><5>>.
Found 1-bit register for signal <x<1><4>>.
Found 1-bit register for signal <x<1><3>>.
Found 1-bit register for signal <x<1><2>>.
Found 1-bit register for signal <x<1><1>>.
Found 1-bit register for signal <x<1><0>>.
Found 1-bit register for signal <en<0>>.
Found 1-bit register for signal <_vga_data>.
Found 1-bit register for signal <y<0><8>>.
Found 1-bit register for signal <y<0><7>>.
Found 1-bit register for signal <y<0><6>>.
Found 1-bit register for signal <y<0><5>>.
Found 1-bit register for signal <y<0><4>>.
Found 1-bit register for signal <y<0><3>>.
Found 1-bit register for signal <y<0><2>>.
Found 1-bit register for signal <y<0><1>>.
Found 1-bit register for signal <y<0><0>>.
Found 1-bit register for signal <y<1><8>>.
Found 1-bit register for signal <y<1><7>>.
Found 1-bit register for signal <y<1><6>>.
Found 1-bit register for signal <y<1><5>>.
Found 1-bit register for signal <y<1><4>>.
Found 1-bit register for signal <y<1><3>>.
Found 1-bit register for signal <y<1><2>>.
Found 1-bit register for signal <y<1><1>>.
Found 1-bit register for signal <y<1><0>>.
Found 10-bit register for signal <random>.
Found 10-bit subtractor for signal <_n0300> created at line 97.
Found 10-bit subtractor for signal <_n0297> created at line 97.
Found 11-bit adder for signal <n0229> created at line 71.
Found 10-bit adder for signal <n0233> created at line 71.
Found 11-bit adder for signal <n0240> created at line 71.
Found 10-bit adder for signal <n0244> created at line 71.
Found 9-bit adder for signal <n0271> created at line 78.
Found 14-bit adder for signal <n0208> created at line 79.
Found 10-bit adder for signal <PWR_21_o_GND_26_o_add_29_OUT> created at line 85.
Found 9-bit adder for signal <n0277> created at line 86.
Found 14-bit adder for signal <n0216> created at line 87.
Found 14-bit adder for signal <n0223> created at line 103.
Found 21-bit adder for signal <cnt[20]_GND_26_o_add_45_OUT> created at line 104.
Found 5-bit subtractor for signal <row[8]_y[0][8]_sub_8_OUT<4:0>> created at line 72.
Found 7-bit subtractor for signal <col[9]_x[0][9]_sub_9_OUT<6:0>> created at line 72.
Found 5-bit subtractor for signal <row[8]_y[1][8]_sub_17_OUT<4:0>> created at line 72.
Found 7-bit subtractor for signal <col[9]_x[1][9]_sub_18_OUT<6:0>> created at line 72.
Found 10x4-bit multiplier for signal <n0272> created at line 79.
Found 10x4-bit multiplier for signal <n0278> created at line 87.
Found 10x4-bit multiplier for signal <n0280> created at line 103.
Found 4096x1-bit Read Only RAM for signal <row[8]_read_port_9_OUT<0>>
Found 4096x1-bit Read Only RAM for signal <row[8]_read_port_18_OUT<0>>
Found 10-bit comparator lessequal for signal <n0002> created at line 71
Found 11-bit comparator greater for signal <GND_26_o_BUS_0001_LessThan_4_o> created at line 71
Found 9-bit comparator lessequal for signal <n0008> created at line 71
Found 10-bit comparator greater for signal <GND_26_o_BUS_0002_LessThan_7_o> created at line 71
Found 10-bit comparator lessequal for signal <n0018> created at line 71
Found 11-bit comparator greater for signal <GND_26_o_BUS_0003_LessThan_13_o> created at line 71
Found 9-bit comparator lessequal for signal <n0024> created at line 71
Found 10-bit comparator greater for signal <GND_26_o_BUS_0004_LessThan_16_o> created at line 71
Found 21-bit comparator equal for signal <cnt[20]_speed[20]_equal_36_o> created at line 90
Summary:
inferred 2 RAM(s).
inferred 3 Multiplier(s).
inferred 17 Adder/Subtractor(s).
inferred 72 D-type flip-flop(s).
inferred 9 Comparator(s).
inferred 73 Multiplexer(s).
Unit <cloud> synthesized.
Synthesizing Unit <mod_10u_3u>.
Related source file is "".
Found 13-bit adder for signal <n0325> created at line 0.
Found 13-bit adder for signal <GND_27_o_b[2]_add_1_OUT> created at line 0.
Found 12-bit adder for signal <n0329> created at line 0.
Found 12-bit adder for signal <GND_27_o_b[2]_add_3_OUT> created at line 0.
Found 11-bit adder for signal <n0333> created at line 0.
Found 11-bit adder for signal <GND_27_o_b[2]_add_5_OUT> created at line 0.
Found 10-bit adder for signal <n0337> created at line 0.
Found 10-bit adder for signal <a[9]_b[2]_add_7_OUT> created at line 0.
Found 10-bit adder for signal <n0341> created at line 0.
Found 10-bit adder for signal <a[9]_GND_27_o_add_9_OUT> created at line 0.
Found 10-bit adder for signal <n0345> created at line 0.
Found 10-bit adder for signal <a[9]_GND_27_o_add_11_OUT> created at line 0.
Found 10-bit adder for signal <n0349> created at line 0.
Found 10-bit adder for signal <a[9]_GND_27_o_add_13_OUT> created at line 0.
Found 10-bit adder for signal <n0353> created at line 0.
Found 10-bit adder for signal <a[9]_GND_27_o_add_15_OUT> created at line 0.
Found 10-bit adder for signal <n0357> created at line 0.
Found 10-bit adder for signal <a[9]_GND_27_o_add_17_OUT> created at line 0.
Found 10-bit adder for signal <n0361> created at line 0.
Found 10-bit adder for signal <a[9]_GND_27_o_add_19_OUT> created at line 0.
Found 10-bit adder for signal <n0365> created at line 0.
Found 10-bit adder for signal <a[9]_GND_27_o_add_21_OUT> created at line 0.
Found 13-bit comparator lessequal for signal <BUS_0001> created at line 0
Found 12-bit comparator lessequal for signal <BUS_0002> created at line 0
Found 11-bit comparator lessequal for signal <BUS_0003> created at line 0
Found 10-bit comparator lessequal for signal <BUS_0004> created at line 0
Found 10-bit comparator lessequal for signal <BUS_0005> created at line 0
Found 10-bit comparator lessequal for signal <BUS_0006> created at line 0
Found 10-bit comparator lessequal for signal <BUS_0007> created at line 0
Found 10-bit comparator lessequal for signal <BUS_0008> created at line 0
Found 10-bit comparator lessequal for signal <BUS_0009> created at line 0
Found 10-bit comparator lessequal for signal <BUS_0010> created at line 0
Found 10-bit comparator lessequal for signal <BUS_0011> created at line 0
Summary:
inferred 22 Adder/Subtractor(s).
inferred 11 Comparator(s).
inferred 101 Multiplexer(s).
Unit <mod_10u_3u> synthesized.
Synthesizing Unit <mod_10u_6u>.
Related source file is "".
Found 16-bit adder for signal <n0355> created at line 0.
Found 16-bit adder for signal <GND_28_o_b[5]_add_1_OUT> created at line 0.
Found 15-bit adder for signal <n0359> created at line 0.
Found 15-bit adder for signal <GND_28_o_b[5]_add_3_OUT> created at line 0.
Found 14-bit adder for signal <n0363> created at line 0.
Found 14-bit adder for signal <GND_28_o_b[5]_add_5_OUT> created at line 0.
Found 13-bit adder for signal <n0367> created at line 0.
Found 13-bit adder for signal <GND_28_o_b[5]_add_7_OUT> created at line 0.
Found 12-bit adder for signal <n0371> created at line 0.
Found 12-bit adder for signal <GND_28_o_b[5]_add_9_OUT> created at line 0.
Found 11-bit adder for signal <n0375> created at line 0.
Found 11-bit adder for signal <GND_28_o_b[5]_add_11_OUT> created at line 0.
Found 10-bit adder for signal <n0379> created at line 0.
Found 10-bit adder for signal <a[9]_b[5]_add_13_OUT> created at line 0.
Found 10-bit adder for signal <n0383> created at line 0.
Found 10-bit adder for signal <a[9]_GND_28_o_add_15_OUT> created at line 0.
Found 10-bit adder for signal <n0387> created at line 0.
Found 10-bit adder for signal <a[9]_GND_28_o_add_17_OUT> created at line 0.
Found 10-bit adder for signal <n0391> created at line 0.
Found 10-bit adder for signal <a[9]_GND_28_o_add_19_OUT> created at line 0.
Found 10-bit adder for signal <n0395> created at line 0.
Found 10-bit adder for signal <a[9]_GND_28_o_add_21_OUT> created at line 0.
Found 16-bit comparator lessequal for signal <BUS_0001> created at line 0
Found 15-bit comparator lessequal for signal <BUS_0002> created at line 0
Found 14-bit comparator lessequal for signal <BUS_0003> created at line 0
Found 13-bit comparator lessequal for signal <BUS_0004> created at line 0
Found 12-bit comparator lessequal for signal <BUS_0005> created at line 0
Found 11-bit comparator lessequal for signal <BUS_0006> created at line 0
Found 10-bit comparator lessequal for signal <BUS_0007> created at line 0
Found 10-bit comparator lessequal for signal <BUS_0008> created at line 0
Found 10-bit comparator lessequal for signal <BUS_0009> created at line 0
Found 10-bit comparator lessequal for signal <BUS_0010> created at line 0
Found 10-bit comparator lessequal for signal <BUS_0011> created at line 0
Summary:
inferred 22 Adder/Subtractor(s).
inferred 11 Comparator(s).
inferred 101 Multiplexer(s).
Unit <mod_10u_6u> synthesized.
Synthesizing Unit <mod_10u_7u>.
Related source file is "".
Found 17-bit adder for signal <GND_30_o_b[6]_add_1_OUT> created at line 0.
Found 16-bit adder for signal <GND_30_o_b[6]_add_3_OUT> created at line 0.
Found 15-bit adder for signal <GND_30_o_b[6]_add_5_OUT> created at line 0.
Found 14-bit adder for signal <GND_30_o_b[6]_add_7_OUT> created at line 0.
Found 13-bit adder for signal <GND_30_o_b[6]_add_9_OUT> created at line 0.
Found 12-bit adder for signal <GND_30_o_b[6]_add_11_OUT> created at line 0.
Found 11-bit adder for signal <GND_30_o_b[6]_add_13_OUT> created at line 0.
Found 10-bit adder for signal <a[9]_b[6]_add_15_OUT> created at line 0.
Found 10-bit adder for signal <a[9]_GND_30_o_add_17_OUT> created at line 0.
Found 10-bit adder for signal <a[9]_GND_30_o_add_19_OUT> created at line 0.
Found 10-bit adder for signal <a[9]_GND_30_o_add_21_OUT> created at line 0.
Found 17-bit comparator lessequal for signal <BUS_0001> created at line 0
Found 16-bit comparator lessequal for signal <BUS_0002> created at line 0
Found 15-bit comparator lessequal for signal <BUS_0003> created at line 0
Found 14-bit comparator lessequal for signal <BUS_0004> created at line 0
Found 13-bit comparator lessequal for signal <BUS_0005> created at line 0
Found 12-bit comparator lessequal for signal <BUS_0006> created at line 0
Found 11-bit comparator lessequal for signal <BUS_0007> created at line 0
Found 10-bit comparator lessequal for signal <BUS_0008> created at line 0
Found 10-bit comparator lessequal for signal <BUS_0009> created at line 0
Found 10-bit comparator lessequal for signal <BUS_0010> created at line 0
Found 10-bit comparator lessequal for signal <BUS_0011> created at line 0
Summary:
inferred 11 Adder/Subtractor(s).
inferred 11 Comparator(s).
inferred 101 Multiplexer(s).
Unit <mod_10u_7u> synthesized.
Synthesizing Unit <dinosaur>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/dinosaur.v".
max_height = 9'b011001000
min_height = 9'b101001001
state_height = 27'b100001110011110000011010111
dino_speed = 32'b00000010011000100101101000000000
WARNING:Xst:647 - Input <clkdiv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2999 - Signal 'rom_data', unconnected in block 'dinosaur', is tied to its initial value.
WARNING:Xst:2999 - Signal 'rom2_data', unconnected in block 'dinosaur', is tied to its initial value.
WARNING:Xst:2999 - Signal 'down_data', unconnected in block 'dinosaur', is tied to its initial value.
Found 21-bit register for signal <count>.
Found 32-bit register for signal <dino_count>.
Found 9-bit register for signal <y>.
Found 1-bit register for signal <jump_flag>.
Found 1-bit register for signal <down_flag>.
Found 1-bit register for signal <dino_flag>.
Found 1-bit register for signal <up_flag>.
Found 12-bit register for signal <vga_data>.
Found 9-bit subtractor for signal <n0128> created at line 37.
Found 9-bit adder for signal <row_add> created at line 37.
Found 32-bit adder for signal <dino_count[31]_GND_32_o_add_4_OUT> created at line 306.
Found 21-bit adder for signal <count[20]_GND_32_o_add_7_OUT> created at line 314.
Found 9-bit adder for signal <y[8]_GND_32_o_add_19_OUT> created at line 343.
Found 9-bit subtractor for signal <GND_32_o_GND_32_o_sub_17_OUT<8:0>> created at line 338.
Found 10-bit subtractor for signal <col_add> created at line 34.
Found 16384x3-bit Read Only RAM for signal <_n16580>
Found 9-bit comparator lessequal for signal <n0017> created at line 315
Found 9-bit comparator lessequal for signal <n0020> created at line 319
Found 9-bit comparator lessequal for signal <n0022> created at line 323
Found 9-bit comparator lessequal for signal <n0024> created at line 327
Found 21-bit comparator equal for signal <count[20]_GND_32_o_equal_18_o> created at line 340
Found 9-bit comparator greater for signal <y[8]_PWR_25_o_LessThan_19_o> created at line 340
Found 10-bit comparator greater for signal <col_add[9]_GND_32_o_LessThan_29_o> created at line 353
Found 9-bit comparator greater for signal <row_add[8]_GND_32_o_LessThan_30_o> created at line 353
Summary:
inferred 1 RAM(s).
inferred 6 Adder/Subtractor(s).
inferred 78 D-type flip-flop(s).
inferred 8 Comparator(s).
inferred 15 Multiplexer(s).
Unit <dinosaur> synthesized.
Synthesizing Unit <bird_cactus>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/bird_cactus.v".
tempvga = 12'b100110011001
bird_speed = 21'b000000000000001100100
WARNING:Xst:647 - Input <clk_div> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2999 - Signal 'bird_data', unconnected in block 'bird_cactus', is tied to its initial value.
WARNING:Xst:2999 - Signal 'bird2_data', unconnected in block 'bird_cactus', is tied to its initial value.
WARNING:Xst:2999 - Signal 'cactus_data', unconnected in block 'bird_cactus', is tied to its initial value.
WARNING:Xst:2999 - Signal 'cactus2_data', unconnected in block 'bird_cactus', is tied to its initial value.
Found 18-bit register for signal <n0237>.
Found 21-bit register for signal <count>.
Found 1-bit register for signal <crash>.
Found 20-bit register for signal <n0234[19:0]>.
Found 18-bit register for signal <n0235[17:0]>.
Found 21-bit register for signal <bird_count>.
Found 1-bit register for signal <bird_flag>.
Found 9-bit register for signal <random>.
Found 1-bit register for signal <graph_type<0><1>>.
Found 1-bit register for signal <graph_type<0><0>>.
Found 1-bit register for signal <graph_type<1><1>>.
Found 1-bit register for signal <graph_type<1><0>>.
Found 12-bit register for signal <vga_data>.
Found 20-bit register for signal <n0236>.
Found 10-bit subtractor for signal <n0346> created at line 241.
Found 9-bit subtractor for signal <n0349> created at line 242.
Found 10-bit subtractor for signal <n0352> created at line 246.
Found 9-bit subtractor for signal <cactus_height[8]_y[0][8]_sub_19_OUT> created at line 247.
Found 10-bit subtractor for signal <n0358> created at line 251.
Found 9-bit subtractor for signal <cactus2_height[8]_y[0][8]_sub_23_OUT> created at line 252.
Found 9-bit subtractor for signal <n0367> created at line 266.
Found 9-bit subtractor for signal <cactus_height[8]_y[1][8]_sub_54_OUT> created at line 271.
Found 9-bit subtractor for signal <cactus2_height[8]_y[1][8]_sub_58_OUT> created at line 276.
Found 10-bit subtractor for signal <x[0][9]_GND_44_o_sub_92_OUT> created at line 331.
Found 10-bit subtractor for signal <x[1][9]_GND_44_o_sub_93_OUT> created at line 332.
Found 10-bit adder for signal <bird_width[9]_x[0][9]_add_12_OUT> created at line 241.
Found 9-bit adder for signal <bird_height[8]_row[8]_add_14_OUT> created at line 242.
Found 10-bit adder for signal <cactus_width[9]_x[0][9]_add_16_OUT> created at line 246.
Found 9-bit adder for signal <cactus_height[8]_row[8]_add_17_OUT> created at line 247.
Found 10-bit adder for signal <cactus2_width[9]_x[0][9]_add_20_OUT> created at line 251.
Found 9-bit adder for signal <cactus2_height[8]_row[8]_add_21_OUT> created at line 252.
Found 10-bit adder for signal <bird_width[9]_x[1][9]_add_47_OUT> created at line 265.
Found 9-bit adder for signal <bird_height[8]_row[8]_add_49_OUT> created at line 266.
Found 10-bit adder for signal <cactus_width[9]_x[1][9]_add_51_OUT> created at line 270.
Found 10-bit adder for signal <cactus2_width[9]_x[1][9]_add_55_OUT> created at line 275.
Found 21-bit adder for signal <count[20]_GND_44_o_add_77_OUT> created at line 290.
Found 21-bit adder for signal <bird_count[20]_GND_44_o_add_93_OUT> created at line 334.
Found 11-bit adder for signal <n0383> created at line 344.
Found 11-bit adder for signal <n0276> created at line 344.
Found 14-bit adder for signal <n0278> created at line 345.
Found 11-bit adder for signal <n0391> created at line 350.
Found 11-bit adder for signal <n0282> created at line 350.
Found 14-bit adder for signal <n0284> created at line 351.
Found 9x5-bit multiplier for signal <n0386> created at line 345.
Found 9x5-bit multiplier for signal <n0394> created at line 351.
Found 4096x1-bit Read Only RAM for signal <row_add[0][5]_read_port_135_OUT<0>>
Found 4096x1-bit Read Only RAM for signal <row_add[1][5]_read_port_163_OUT<0>>
Found 4x3-bit Read Only RAM for signal <_n0498[0:2]>
Found 4x3-bit Read Only RAM for signal <_n0503[0:2]>
Found 8192x3-bit Read Only RAM for signal <_n8696>
Found 8192x3-bit Read Only RAM for signal <_n16889>
Found 1-bit 3-to-1 multiplexer for signal <graph_type[0][1]_cactus2_width[9]_Mux_23_o> created at line 233.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[0][1]_cactus2_width[9]_Mux_24_o> created at line 233.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[0][1]_cactus2_width[9]_Mux_25_o> created at line 233.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[0][1]_cactus2_width[9]_Mux_26_o> created at line 233.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[0][1]_cactus2_width[9]_Mux_27_o> created at line 233.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[0][1]_cactus2_width[9]_Mux_28_o> created at line 233.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[0][1]_cactus2_width[9]_Mux_29_o> created at line 233.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[0][1]_cactus2_width[9]_Mux_30_o> created at line 233.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[0][1]_cactus2_width[9]_Mux_31_o> created at line 233.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[0][1]_cactus2_width[9]_Mux_32_o> created at line 233.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[0][1]_cactus2_height[8]_Mux_33_o> created at line 233.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[0][1]_cactus2_height[8]_Mux_34_o> created at line 233.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[0][1]_cactus2_height[8]_Mux_35_o> created at line 233.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[0][1]_cactus2_height[8]_Mux_36_o> created at line 233.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[0][1]_cactus2_height[8]_Mux_37_o> created at line 233.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[0][1]_cactus2_height[8]_Mux_38_o> created at line 233.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[0][1]_cactus2_height[8]_Mux_39_o> created at line 233.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[0][1]_cactus2_height[8]_Mux_40_o> created at line 233.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[0][1]_cactus2_height[8]_Mux_41_o> created at line 233.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[1][1]_cactus2_width[9]_Mux_58_o> created at line 257.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[1][1]_cactus2_width[9]_Mux_59_o> created at line 257.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[1][1]_cactus2_width[9]_Mux_60_o> created at line 257.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[1][1]_cactus2_width[9]_Mux_61_o> created at line 257.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[1][1]_cactus2_width[9]_Mux_62_o> created at line 257.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[1][1]_cactus2_width[9]_Mux_63_o> created at line 257.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[1][1]_cactus2_width[9]_Mux_64_o> created at line 257.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[1][1]_cactus2_width[9]_Mux_65_o> created at line 257.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[1][1]_cactus2_width[9]_Mux_66_o> created at line 257.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[1][1]_cactus2_width[9]_Mux_67_o> created at line 257.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[1][1]_cactus2_height[8]_Mux_68_o> created at line 257.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[1][1]_cactus2_height[8]_Mux_69_o> created at line 257.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[1][1]_cactus2_height[8]_Mux_70_o> created at line 257.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[1][1]_cactus2_height[8]_Mux_71_o> created at line 257.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[1][1]_cactus2_height[8]_Mux_72_o> created at line 257.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[1][1]_cactus2_height[8]_Mux_73_o> created at line 257.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[1][1]_cactus2_height[8]_Mux_74_o> created at line 257.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[1][1]_cactus2_height[8]_Mux_75_o> created at line 257.
Found 1-bit 3-to-1 multiplexer for signal <graph_type[1][1]_cactus2_height[8]_Mux_76_o> created at line 257.
Found 1-bit 4-to-1 multiplexer for signal <graph_type[0][1]_crash_Mux_145_o> created at line 357.
Found 12-bit 3-to-1 multiplexer for signal <graph_type[0][1]_PWR_26_o_wide_mux_146_OUT> created at line 357.
Found 1-bit 4-to-1 multiplexer for signal <graph_type[0][1]_graph_type[0][1]_Mux_173_o> created at line 448.
Found 12-bit 3-to-1 multiplexer for signal <graph_type[0][1]_graph_type[0][1]_wide_mux_174_OUT> created at line 448.
Found 21-bit comparator equal for signal <count[20]_speed[20]_equal_91_o> created at line 329
Found 10-bit comparator greater for signal <col_add[0][9]_bird_width[9]_LessThan_127_o> created at line 383
Found 9-bit comparator greater for signal <row_add[0][8]_bird_height[8]_LessThan_128_o> created at line 383
Found 10-bit comparator greater for signal <col_add[0][9]_cactus_width[9]_LessThan_134_o> created at line 404
Found 9-bit comparator greater for signal <row_add[0][8]_cactus_height[8]_LessThan_135_o> created at line 404
Found 10-bit comparator greater for signal <col_add[0][9]_cactus2_width[9]_LessThan_140_o> created at line 425
Found 9-bit comparator greater for signal <row_add[0][8]_cactus2_height[8]_LessThan_141_o> created at line 425
Found 10-bit comparator greater for signal <col_add[1][9]_bird_width[9]_LessThan_155_o> created at line 467
Found 9-bit comparator greater for signal <row_add[1][8]_bird_height[8]_LessThan_156_o> created at line 467
Found 10-bit comparator greater for signal <col_add[1][9]_cactus_width[9]_LessThan_162_o> created at line 481
Found 9-bit comparator greater for signal <row_add[1][8]_cactus_height[8]_LessThan_163_o> created at line 481
Found 10-bit comparator greater for signal <col_add[1][9]_cactus2_width[9]_LessThan_168_o> created at line 494
Found 9-bit comparator greater for signal <row_add[1][8]_cactus2_height[8]_LessThan_169_o> created at line 494
Summary:
inferred 6 RAM(s).
inferred 2 Multiplier(s).
inferred 29 Adder/Subtractor(s).
inferred 145 D-type flip-flop(s).
inferred 13 Comparator(s).
inferred 123 Multiplexer(s).
Unit <bird_cactus> synthesized.
Synthesizing Unit <mod_9u_8u>.
Related source file is "".
Found 17-bit adder for signal <n0337> created at line 0.
Found 17-bit adder for signal <GND_45_o_b[7]_add_1_OUT> created at line 0.
Found 16-bit adder for signal <n0341> created at line 0.
Found 16-bit adder for signal <GND_45_o_b[7]_add_3_OUT> created at line 0.
Found 15-bit adder for signal <n0345> created at line 0.
Found 15-bit adder for signal <GND_45_o_b[7]_add_5_OUT> created at line 0.
Found 14-bit adder for signal <n0349> created at line 0.
Found 14-bit adder for signal <GND_45_o_b[7]_add_7_OUT> created at line 0.
Found 13-bit adder for signal <n0353> created at line 0.
Found 13-bit adder for signal <GND_45_o_b[7]_add_9_OUT> created at line 0.
Found 12-bit adder for signal <n0357> created at line 0.
Found 12-bit adder for signal <GND_45_o_b[7]_add_11_OUT> created at line 0.
Found 11-bit adder for signal <n0361> created at line 0.
Found 11-bit adder for signal <GND_45_o_b[7]_add_13_OUT> created at line 0.
Found 10-bit adder for signal <n0365> created at line 0.
Found 10-bit adder for signal <GND_45_o_b[7]_add_15_OUT> created at line 0.
Found 9-bit adder for signal <n0369> created at line 0.
Found 9-bit adder for signal <a[8]_b[7]_add_17_OUT> created at line 0.
Found 9-bit adder for signal <n0373> created at line 0.
Found 9-bit adder for signal <a[8]_GND_45_o_add_19_OUT> created at line 0.
Found 17-bit comparator lessequal for signal <BUS_0001> created at line 0
Found 16-bit comparator lessequal for signal <BUS_0002> created at line 0
Found 15-bit comparator lessequal for signal <BUS_0003> created at line 0
Found 14-bit comparator lessequal for signal <BUS_0004> created at line 0
Found 13-bit comparator lessequal for signal <BUS_0005> created at line 0
Found 12-bit comparator lessequal for signal <BUS_0006> created at line 0
Found 11-bit comparator lessequal for signal <BUS_0007> created at line 0
Found 10-bit comparator lessequal for signal <BUS_0008> created at line 0
Found 9-bit comparator lessequal for signal <BUS_0009> created at line 0
Found 9-bit comparator lessequal for signal <BUS_0010> created at line 0
Summary:
inferred 20 Adder/Subtractor(s).
inferred 10 Comparator(s).
inferred 82 Multiplexer(s).
Unit <mod_9u_8u> synthesized.
Synthesizing Unit <gameover>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/gameover.v".
WARNING:Xst:647 - Input <clkdiv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2999 - Signal 'rom_data', unconnected in block 'gameover', is tied to its initial value.
Found 10-bit subtractor for signal <col_add> created at line 32.
Found 9-bit subtractor for signal <row_add> created at line 33.
Found 131072x1-bit Read Only RAM for signal <row_add[7]_read_port_8_OUT<0>>
Found 10-bit comparator greater for signal <col_add[9]_GND_47_o_LessThan_7_o> created at line 248
Found 9-bit comparator greater for signal <row_add[8]_GND_47_o_LessThan_8_o> created at line 248
Summary:
inferred 1 RAM(s).
inferred 2 Adder/Subtractor(s).
inferred 2 Comparator(s).
inferred 2 Multiplexer(s).
Unit <gameover> synthesized.
Synthesizing Unit <night>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/night.v".
Found 1-bit register for signal <night>.
Found 21-bit register for signal <grade>.
Found 12-bit register for signal <vga_data>.
Found 32-bit register for signal <count>.
Found 32-bit adder for signal <count[31]_GND_69_o_add_1_OUT> created at line 31.
Found 21-bit adder for signal <grade[20]_GND_69_o_add_5_OUT> created at line 41.
Found 32-bit comparator greater for signal <GND_69_o_count[31]_LessThan_5_o> created at line 38
Found 21-bit comparator greater for signal <GND_69_o_grade[20]_LessThan_9_o> created at line 43
Summary:
inferred 2 Adder/Subtractor(s).
inferred 66 D-type flip-flop(s).
inferred 2 Comparator(s).
inferred 3 Multiplexer(s).
Unit <night> synthesized.
Synthesizing Unit <ctrl>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/ctrl.v".
Found 1-bit register for signal <show>.
Found 1-bit register for signal <jump>.
Found 32-bit register for signal <count>.
Found 1-bit register for signal <crash_flag>.
Found 32-bit adder for signal <count[31]_GND_70_o_add_3_OUT> created at line 46.
Found 32-bit comparator greater for signal <GND_70_o_count[31]_LessThan_5_o> created at line 47
Found 32-bit comparator greater for signal <GND_70_o_count[31]_LessThan_6_o> created at line 51
Summary:
inferred 1 Adder/Subtractor(s).
inferred 35 D-type flip-flop(s).
inferred 2 Comparator(s).
inferred 3 Multiplexer(s).
Unit <ctrl> synthesized.
Synthesizing Unit <grade>.
Related source file is "/home/wxxcl/ISE_workspace/DinoGame/grade.v".
Found 21-bit register for signal <grade>.
Found 32-bit register for signal <count>.
Found 32-bit adder for signal <count[31]_GND_71_o_add_1_OUT> created at line 29.
Found 21-bit adder for signal <grade[20]_GND_71_o_add_4_OUT> created at line 37.
Found 32-bit comparator greater for signal <GND_71_o_count[31]_LessThan_4_o> created at line 34
Summary:
inferred 2 Adder/Subtractor(s).
inferred 53 D-type flip-flop(s).
inferred 1 Comparator(s).
Unit <grade> synthesized.
Synthesizing Unit <mod_21u_4u>.
Related source file is "".
Found 25-bit adder for signal <n1125> created at line 0.
Found 25-bit adder for signal <GND_72_o_b[3]_add_1_OUT> created at line 0.
Found 24-bit adder for signal <n1129> created at line 0.
Found 24-bit adder for signal <GND_72_o_b[3]_add_3_OUT> created at line 0.
Found 23-bit adder for signal <n1133> created at line 0.
Found 23-bit adder for signal <GND_72_o_b[3]_add_5_OUT> created at line 0.
Found 22-bit adder for signal <n1137> created at line 0.
Found 22-bit adder for signal <GND_72_o_b[3]_add_7_OUT> created at line 0.
Found 21-bit adder for signal <n1141> created at line 0.
Found 21-bit adder for signal <a[20]_b[3]_add_9_OUT> created at line 0.
Found 21-bit adder for signal <n1145> created at line 0.
Found 21-bit adder for signal <a[20]_GND_72_o_add_11_OUT> created at line 0.
Found 21-bit adder for signal <n1149> created at line 0.
Found 21-bit adder for signal <a[20]_GND_72_o_add_13_OUT> created at line 0.
Found 21-bit adder for signal <n1153> created at line 0.
Found 21-bit adder for signal <a[20]_GND_72_o_add_15_OUT> created at line 0.
Found 21-bit adder for signal <n1157> created at line 0.
Found 21-bit adder for signal <a[20]_GND_72_o_add_17_OUT> created at line 0.
Found 21-bit adder for signal <n1161> created at line 0.
Found 21-bit adder for signal <a[20]_GND_72_o_add_19_OUT> created at line 0.
Found 21-bit adder for signal <n1165> created at line 0.
Found 21-bit adder for signal <a[20]_GND_72_o_add_21_OUT> created at line 0.
Found 21-bit adder for signal <n1169> created at line 0.
Found 21-bit adder for signal <a[20]_GND_72_o_add_23_OUT> created at line 0.
Found 21-bit adder for signal <n1173> created at line 0.
Found 21-bit adder for signal <a[20]_GND_72_o_add_25_OUT> created at line 0.
Found 21-bit adder for signal <n1177> created at line 0.
Found 21-bit adder for signal <a[20]_GND_72_o_add_27_OUT> created at line 0.
Found 21-bit adder for signal <n1181> created at line 0.
Found 21-bit adder for signal <a[20]_GND_72_o_add_29_OUT> created at line 0.
Found 21-bit adder for signal <n1185> created at line 0.
Found 21-bit adder for signal <a[20]_GND_72_o_add_31_OUT> created at line 0.
Found 21-bit adder for signal <n1189> created at line 0.
Found 21-bit adder for signal <a[20]_GND_72_o_add_33_OUT> created at line 0.
Found 21-bit adder for signal <n1193> created at line 0.
Found 21-bit adder for signal <a[20]_GND_72_o_add_35_OUT> created at line 0.
Found 21-bit adder for signal <n1197> created at line 0.
Found 21-bit adder for signal <a[20]_GND_72_o_add_37_OUT> created at line 0.
Found 21-bit adder for signal <n1201> created at line 0.
Found 21-bit adder for signal <a[20]_GND_72_o_add_39_OUT> created at line 0.
Found 21-bit adder for signal <n1205> created at line 0.
Found 21-bit adder for signal <a[20]_GND_72_o_add_41_OUT> created at line 0.
Found 21-bit adder for signal <n1209> created at line 0.
Found 21-bit adder for signal <a[20]_GND_72_o_add_43_OUT> created at line 0.
Found 25-bit comparator lessequal for signal <BUS_0001> created at line 0
Found 24-bit comparator lessequal for signal <BUS_0002> created at line 0
Found 23-bit comparator lessequal for signal <BUS_0003> created at line 0
Found 22-bit comparator lessequal for signal <BUS_0004> created at line 0
Found 21-bit comparator lessequal for signal <BUS_0005> created at line 0
Found 21-bit comparator lessequal for signal <BUS_0006> created at line 0
Found 21-bit comparator lessequal for signal <BUS_0007> created at line 0
Found 21-bit comparator lessequal for signal <BUS_0008> created at line 0
Found 21-bit comparator lessequal for signal <BUS_0009> created at line 0
Found 21-bit comparator lessequal for signal <BUS_0010> created at line 0
Found 21-bit comparator lessequal for signal <BUS_0011> created at line 0
Found 21-bit comparator lessequal for signal <BUS_0012> created at line 0
Found 21-bit comparator lessequal for signal <BUS_0013> created at line 0