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[ELF] Pass Ctx & to check*
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16 files changed

+182
-180
lines changed

16 files changed

+182
-180
lines changed

‎lld/ELF/Arch/AArch64.cpp‎

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -484,17 +484,17 @@ void AArch64::relocate(uint8_t *loc, const Relocation &rel,
484484
switch (rel.type) {
485485
case R_AARCH64_ABS16:
486486
case R_AARCH64_PREL16:
487-
checkIntUInt(loc, val, 16, rel);
487+
checkIntUInt(ctx, loc, val, 16, rel);
488488
write16(ctx, loc, val);
489489
break;
490490
case R_AARCH64_ABS32:
491491
case R_AARCH64_PREL32:
492-
checkIntUInt(loc, val, 32, rel);
492+
checkIntUInt(ctx, loc, val, 32, rel);
493493
write32(ctx, loc, val);
494494
break;
495495
case R_AARCH64_PLT32:
496496
case R_AARCH64_GOTPCREL32:
497-
checkInt(loc, val, 32, rel);
497+
checkInt(ctx, loc, val, 32, rel);
498498
write32(ctx, loc, val);
499499
break;
500500
case R_AARCH64_ABS64:
@@ -535,13 +535,13 @@ void AArch64::relocate(uint8_t *loc, const Relocation &rel,
535535
case R_AARCH64_ADR_PREL_PG_HI21:
536536
case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
537537
case R_AARCH64_TLSDESC_ADR_PAGE21:
538-
checkInt(loc, val, 33, rel);
538+
checkInt(ctx, loc, val, 33, rel);
539539
[[fallthrough]];
540540
case R_AARCH64_ADR_PREL_PG_HI21_NC:
541541
write32AArch64Addr(loc, val >> 12);
542542
break;
543543
case R_AARCH64_ADR_PREL_LO21:
544-
checkInt(loc, val, 21, rel);
544+
checkInt(ctx, loc, val, 21, rel);
545545
write32AArch64Addr(loc, val);
546546
break;
547547
case R_AARCH64_JUMP26:
@@ -555,14 +555,14 @@ void AArch64::relocate(uint8_t *loc, const Relocation &rel,
555555
write32le(loc, 0x14000000);
556556
[[fallthrough]];
557557
case R_AARCH64_CALL26:
558-
checkInt(loc, val, 28, rel);
558+
checkInt(ctx, loc, val, 28, rel);
559559
writeMaskedBits32le(loc, (val & 0x0FFFFFFC) >> 2, 0x0FFFFFFC >> 2);
560560
break;
561561
case R_AARCH64_CONDBR19:
562562
case R_AARCH64_LD_PREL_LO19:
563563
case R_AARCH64_GOT_LD_PREL19:
564-
checkAlignment(loc, val, 4, rel);
565-
checkInt(loc, val, 21, rel);
564+
checkAlignment(ctx, loc, val, 4, rel);
565+
checkInt(ctx, loc, val, 21, rel);
566566
writeMaskedBits32le(loc, (val & 0x1FFFFC) << 3, 0x1FFFFC << 3);
567567
break;
568568
case R_AARCH64_LDST8_ABS_LO12_NC:
@@ -571,45 +571,45 @@ void AArch64::relocate(uint8_t *loc, const Relocation &rel,
571571
break;
572572
case R_AARCH64_LDST16_ABS_LO12_NC:
573573
case R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
574-
checkAlignment(loc, val, 2, rel);
574+
checkAlignment(ctx, loc, val, 2, rel);
575575
write32Imm12(loc, getBits(val, 1, 11));
576576
break;
577577
case R_AARCH64_LDST32_ABS_LO12_NC:
578578
case R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
579-
checkAlignment(loc, val, 4, rel);
579+
checkAlignment(ctx, loc, val, 4, rel);
580580
write32Imm12(loc, getBits(val, 2, 11));
581581
break;
582582
case R_AARCH64_LDST64_ABS_LO12_NC:
583583
case R_AARCH64_LD64_GOT_LO12_NC:
584584
case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
585585
case R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
586586
case R_AARCH64_TLSDESC_LD64_LO12:
587-
checkAlignment(loc, val, 8, rel);
587+
checkAlignment(ctx, loc, val, 8, rel);
588588
write32Imm12(loc, getBits(val, 3, 11));
589589
break;
590590
case R_AARCH64_LDST128_ABS_LO12_NC:
591591
case R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC:
592-
checkAlignment(loc, val, 16, rel);
592+
checkAlignment(ctx, loc, val, 16, rel);
593593
write32Imm12(loc, getBits(val, 4, 11));
594594
break;
595595
case R_AARCH64_LD64_GOTPAGE_LO15:
596-
checkAlignment(loc, val, 8, rel);
596+
checkAlignment(ctx, loc, val, 8, rel);
597597
write32Imm12(loc, getBits(val, 3, 14));
598598
break;
599599
case R_AARCH64_MOVW_UABS_G0:
600-
checkUInt(loc, val, 16, rel);
600+
checkUInt(ctx, loc, val, 16, rel);
601601
[[fallthrough]];
602602
case R_AARCH64_MOVW_UABS_G0_NC:
603603
writeMaskedBits32le(loc, (val & 0xFFFF) << 5, 0xFFFF << 5);
604604
break;
605605
case R_AARCH64_MOVW_UABS_G1:
606-
checkUInt(loc, val, 32, rel);
606+
checkUInt(ctx, loc, val, 32, rel);
607607
[[fallthrough]];
608608
case R_AARCH64_MOVW_UABS_G1_NC:
609609
writeMaskedBits32le(loc, (val & 0xFFFF0000) >> 11, 0xFFFF0000 >> 11);
610610
break;
611611
case R_AARCH64_MOVW_UABS_G2:
612-
checkUInt(loc, val, 48, rel);
612+
checkUInt(ctx, loc, val, 48, rel);
613613
[[fallthrough]];
614614
case R_AARCH64_MOVW_UABS_G2_NC:
615615
writeMaskedBits32le(loc, (val & 0xFFFF00000000) >> 27,
@@ -622,7 +622,7 @@ void AArch64::relocate(uint8_t *loc, const Relocation &rel,
622622
case R_AARCH64_MOVW_PREL_G0:
623623
case R_AARCH64_MOVW_SABS_G0:
624624
case R_AARCH64_TLSLE_MOVW_TPREL_G0:
625-
checkInt(loc, val, 17, rel);
625+
checkInt(ctx, loc, val, 17, rel);
626626
[[fallthrough]];
627627
case R_AARCH64_MOVW_PREL_G0_NC:
628628
case R_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
@@ -631,7 +631,7 @@ void AArch64::relocate(uint8_t *loc, const Relocation &rel,
631631
case R_AARCH64_MOVW_PREL_G1:
632632
case R_AARCH64_MOVW_SABS_G1:
633633
case R_AARCH64_TLSLE_MOVW_TPREL_G1:
634-
checkInt(loc, val, 33, rel);
634+
checkInt(ctx, loc, val, 33, rel);
635635
[[fallthrough]];
636636
case R_AARCH64_MOVW_PREL_G1_NC:
637637
case R_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
@@ -640,7 +640,7 @@ void AArch64::relocate(uint8_t *loc, const Relocation &rel,
640640
case R_AARCH64_MOVW_PREL_G2:
641641
case R_AARCH64_MOVW_SABS_G2:
642642
case R_AARCH64_TLSLE_MOVW_TPREL_G2:
643-
checkInt(loc, val, 49, rel);
643+
checkInt(ctx, loc, val, 49, rel);
644644
[[fallthrough]];
645645
case R_AARCH64_MOVW_PREL_G2_NC:
646646
writeSMovWImm(loc, val >> 32);
@@ -649,11 +649,11 @@ void AArch64::relocate(uint8_t *loc, const Relocation &rel,
649649
writeSMovWImm(loc, val >> 48);
650650
break;
651651
case R_AARCH64_TSTBR14:
652-
checkInt(loc, val, 16, rel);
652+
checkInt(ctx, loc, val, 16, rel);
653653
writeMaskedBits32le(loc, (val & 0xFFFC) << 3, 0xFFFC << 3);
654654
break;
655655
case R_AARCH64_TLSLE_ADD_TPREL_HI12:
656-
checkUInt(loc, val, 24, rel);
656+
checkUInt(ctx, loc, val, 24, rel);
657657
write32Imm12(loc, val >> 12);
658658
break;
659659
case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
@@ -682,7 +682,7 @@ void AArch64::relaxTlsGdToLe(uint8_t *loc, const Relocation &rel,
682682
// movk x0, #0x10
683683
// nop
684684
// nop
685-
checkUInt(loc, val, 32, rel);
685+
checkUInt(ctx, loc, val, 32, rel);
686686

687687
switch (rel.type) {
688688
case R_AARCH64_TLSDESC_ADD_LO12:
@@ -734,7 +734,7 @@ void AArch64::relaxTlsGdToIe(uint8_t *loc, const Relocation &rel,
734734

735735
void AArch64::relaxTlsIeToLe(uint8_t *loc, const Relocation &rel,
736736
uint64_t val) const {
737-
checkUInt(loc, val, 32, rel);
737+
checkUInt(ctx, loc, val, 32, rel);
738738

739739
if (rel.type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) {
740740
// Generate MOVZ.

‎lld/ELF/Arch/AMDGPU.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -167,7 +167,7 @@ void AMDGPU::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
167167
break;
168168
case R_AMDGPU_REL16: {
169169
int64_t simm = (static_cast<int64_t>(val) - 4) / 4;
170-
checkInt(loc, simm, 16, rel);
170+
checkInt(ctx, loc, simm, 16, rel);
171171
write16le(loc, simm);
172172
break;
173173
}

‎lld/ELF/Arch/ARM.cpp‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -576,7 +576,7 @@ static void encodeLdrGroup(Ctx &ctx, uint8_t *loc, const Relocation &rel,
576576
val = -val;
577577
}
578578
uint32_t imm = getRemAndLZForGroup(group, val).first;
579-
checkUInt(loc, imm, 12, rel);
579+
checkUInt(ctx, loc, imm, 12, rel);
580580
write32(ctx, loc, (read32(ctx, loc) & 0xff7ff000) | opcode | imm);
581581
}
582582

@@ -594,7 +594,7 @@ static void encodeLdrsGroup(Ctx &ctx, uint8_t *loc, const Relocation &rel,
594594
val = -val;
595595
}
596596
uint32_t imm = getRemAndLZForGroup(group, val).first;
597-
checkUInt(loc, imm, 8, rel);
597+
checkUInt(ctx, loc, imm, 8, rel);
598598
write32(ctx, loc,
599599
(read32(ctx, loc) & 0xff7ff0f0) | opcode | ((imm & 0xf0) << 4) |
600600
(imm & 0xf));
@@ -622,7 +622,7 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
622622
write32(ctx, loc, val);
623623
break;
624624
case R_ARM_PREL31:
625-
checkInt(loc, val, 31, rel);
625+
checkInt(ctx, loc, val, 31, rel);
626626
write32(ctx, loc, (read32(ctx, loc) & 0x80000000) | (val & ~0x80000000));
627627
break;
628628
case R_ARM_CALL: {
@@ -639,7 +639,7 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
639639
stateChangeWarning(ctx, loc, rel.type, *rel.sym);
640640
if (rel.sym->isFunc() ? bit0Thumb : isBlx) {
641641
// The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1'
642-
checkInt(loc, val, 26, rel);
642+
checkInt(ctx, loc, val, 26, rel);
643643
write32(ctx, loc,
644644
0xfa000000 | // opcode
645645
((val & 2) << 23) | // H
@@ -655,23 +655,23 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
655655
case R_ARM_JUMP24:
656656
case R_ARM_PC24:
657657
case R_ARM_PLT32:
658-
checkInt(loc, val, 26, rel);
658+
checkInt(ctx, loc, val, 26, rel);
659659
write32(ctx, loc,
660660
(read32(ctx, loc) & ~0x00ffffff) | ((val >> 2) & 0x00ffffff));
661661
break;
662662
case R_ARM_THM_JUMP8:
663663
// We do a 9 bit check because val is right-shifted by 1 bit.
664-
checkInt(loc, val, 9, rel);
664+
checkInt(ctx, loc, val, 9, rel);
665665
write16(ctx, loc, (read32(ctx, loc) & 0xff00) | ((val >> 1) & 0x00ff));
666666
break;
667667
case R_ARM_THM_JUMP11:
668668
// We do a 12 bit check because val is right-shifted by 1 bit.
669-
checkInt(loc, val, 12, rel);
669+
checkInt(ctx, loc, val, 12, rel);
670670
write16(ctx, loc, (read32(ctx, loc) & 0xf800) | ((val >> 1) & 0x07ff));
671671
break;
672672
case R_ARM_THM_JUMP19:
673673
// Encoding T3: Val = S:J2:J1:imm6:imm11:0
674-
checkInt(loc, val, 21, rel);
674+
checkInt(ctx, loc, val, 21, rel);
675675
write16(ctx, loc,
676676
(read16(ctx, loc) & 0xfbc0) | // opcode cond
677677
((val >> 10) & 0x0400) | // S
@@ -708,7 +708,7 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
708708
if (!ctx.arg.armJ1J2BranchEncoding) {
709709
// Older Arm architectures do not support R_ARM_THM_JUMP24 and have
710710
// different encoding rules and range due to J1 and J2 always being 1.
711-
checkInt(loc, val, 23, rel);
711+
checkInt(ctx, loc, val, 23, rel);
712712
write16(ctx, loc,
713713
0xf000 | // opcode
714714
((val >> 12) & 0x07ff)); // imm11
@@ -723,7 +723,7 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
723723
[[fallthrough]];
724724
case R_ARM_THM_JUMP24:
725725
// Encoding B T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0
726-
checkInt(loc, val, 25, rel);
726+
checkInt(ctx, loc, val, 25, rel);
727727
write16(ctx, loc,
728728
0xf000 | // opcode
729729
((val >> 14) & 0x0400) | // S
@@ -829,7 +829,7 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
829829
imm = -imm;
830830
sub = 0x00a0;
831831
}
832-
checkUInt(loc, imm, 12, rel);
832+
checkUInt(ctx, loc, imm, 12, rel);
833833
write16(ctx, loc, (read16(ctx, loc) & 0xfb0f) | sub | (imm & 0x800) >> 1);
834834
write16(ctx, loc + 2,
835835
(read16(ctx, loc + 2) & 0x8f00) | (imm & 0x700) << 4 |
@@ -843,8 +843,8 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
843843
// bottom bit to recover S + A - Pa.
844844
if (rel.sym->isFunc())
845845
val &= ~0x1;
846-
checkUInt(loc, val, 10, rel);
847-
checkAlignment(loc, val, 4, rel);
846+
checkUInt(ctx, loc, val, 10, rel);
847+
checkAlignment(ctx, loc, val, 4, rel);
848848
write16(ctx, loc, (read16(ctx, loc) & 0xff00) | (val & 0x3fc) >> 2);
849849
break;
850850
case R_ARM_THM_PC12: {
@@ -861,7 +861,7 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
861861
imm12 = -imm12;
862862
u = 0;
863863
}
864-
checkUInt(loc, imm12, 12, rel);
864+
checkUInt(ctx, loc, imm12, 12, rel);
865865
write16(ctx, loc, read16(ctx, loc) | u);
866866
write16(ctx, loc + 2, (read16(ctx, loc + 2) & 0xf000) | imm12);
867867
break;

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