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[MC] Don't print () around $ names
This MIPS behavior from edb9d84 (2010) is obsoleted and misleading. This caused confusion in https://reviews.llvm.org/D123702 ([NVPTX] Disable parens for identifiers starting with '$') Note: $tmp was rejected by AsmParser before https://reviews.llvm.org/D75111 (2020)
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57 files changed

+227
-245
lines changed

‎llvm/include/llvm/MC/MCAsmInfo.h‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -650,9 +650,6 @@ class MCAsmInfo {
650650
bool doDwarfFDESymbolsUseAbsDiff() const { return DwarfFDESymbolsUseAbsDiff; }
651651
bool useDwarfRegNumForCFI() const { return DwarfRegNumForCFI; }
652652
bool useParensForSymbolVariant() const { return UseParensForSymbolVariant; }
653-
bool useParensForDollarSignNames() const {
654-
return UseParensForDollarSignNames;
655-
}
656653
bool supportsExtendedDwarfLocDirective() const {
657654
return SupportsExtendedDwarfLocDirective;
658655
}

‎llvm/include/llvm/MC/MCExpr.h‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -81,8 +81,7 @@ class MCExpr {
8181
/// \name Utility Methods
8282
/// @{
8383

84-
void print(raw_ostream &OS, const MCAsmInfo *MAI,
85-
bool InParens = false) const;
84+
void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
8685
void dump() const;
8786

8887
/// Returns whether the given symbol is used anywhere in the expression or

‎llvm/lib/MC/MCExpr.cpp‎

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ STATISTIC(MCExprEvaluate, "Number of MCExpr evaluations");
4040
// VariantKind printing and formatting utilize MAI. operator<< (dump and some
4141
// target code) specifies MAI as nullptr and should be avoided when MAI is
4242
// needed.
43-
void MCExpr::print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens) const {
43+
void MCExpr::print(raw_ostream &OS, const MCAsmInfo *MAI) const {
4444
switch (getKind()) {
4545
case MCExpr::Target:
4646
return cast<MCTargetExpr>(this)->printImpl(OS, MAI);
@@ -75,17 +75,7 @@ void MCExpr::print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens) const {
7575
case MCExpr::SymbolRef: {
7676
const MCSymbolRefExpr &SRE = cast<MCSymbolRefExpr>(*this);
7777
const MCSymbol &Sym = SRE.getSymbol();
78-
// Parenthesize names that start with $ so that they don't look like
79-
// absolute names.
80-
bool UseParens = MAI && MAI->useParensForDollarSignNames() && !InParens &&
81-
Sym.getName().starts_with('$');
82-
83-
if (UseParens) {
84-
OS << '(';
85-
Sym.print(OS, MAI);
86-
OS << ')';
87-
} else
88-
Sym.print(OS, MAI);
78+
Sym.print(OS, MAI);
8979

9080
const MCSymbolRefExpr::VariantKind Kind = SRE.getKind();
9181
if (Kind != MCSymbolRefExpr::VK_None) {

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,7 @@ void AMDGPUMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
7777
break;
7878
}
7979
for (const auto *It = Args.begin(); It != Args.end(); ++It) {
80-
(*It)->print(OS, MAI, /*InParens=*/false);
80+
(*It)->print(OS, MAI);
8181
if ((It + 1) != Args.end())
8282
OS << ", ";
8383
}

‎llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -138,7 +138,7 @@ void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
138138
}
139139

140140
assert(Op.isExpr() && "unknown operand kind in printOperand");
141-
Op.getExpr()->print(O, &MAI, true);
141+
Op.getExpr()->print(O, &MAI);
142142
}
143143

144144
void MipsInstPrinter::printJumpOperand(const MCInst *MI, unsigned OpNo,

‎llvm/lib/Target/Mips/MCTargetDesc/MipsMCExpr.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@ void MipsMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
4545
case MEK_DTPREL:
4646
// MEK_DTPREL is used for marking TLS DIEExpr only
4747
// and contains a regular sub-expression.
48-
getSubExpr()->print(OS, MAI, true);
48+
getSubExpr()->print(OS, MAI);
4949
return;
5050
case MEK_CALL_HI16:
5151
OS << "%call_hi";
@@ -125,7 +125,7 @@ void MipsMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
125125
if (Expr->evaluateAsAbsolute(AbsVal))
126126
OS << AbsVal;
127127
else
128-
Expr->print(OS, MAI, true);
128+
Expr->print(OS, MAI);
129129
OS << ')';
130130
}
131131

‎llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -58,10 +58,6 @@ NVPTXMCAsmInfo::NVPTXMCAsmInfo(const Triple &TheTriple,
5858

5959
UseIntegratedAssembler = false;
6060

61-
// Avoid using parens for identifiers starting with $ - ptxas does
62-
// not expect them.
63-
UseParensForDollarSignNames = false;
64-
6561
// ptxas does not support DWARF `.file fileno directory filename'
6662
// syntax as of v11.X.
6763
EnableDwarfFileDirectoryDefault = false;

‎llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -100,7 +100,7 @@ void XtensaInstPrinter::printBranchTarget(const MCInst *MI, int OpNum,
100100
OS << '+';
101101
OS << Val;
102102
} else if (MC.isExpr())
103-
MC.getExpr()->print(OS, &MAI, true);
103+
MC.getExpr()->print(OS, &MAI);
104104
else
105105
llvm_unreachable("Invalid operand");
106106
}
@@ -115,7 +115,7 @@ void XtensaInstPrinter::printJumpTarget(const MCInst *MI, int OpNum,
115115
OS << '+';
116116
OS << Val;
117117
} else if (MC.isExpr())
118-
MC.getExpr()->print(OS, &MAI, true);
118+
MC.getExpr()->print(OS, &MAI);
119119
else
120120
llvm_unreachable("Invalid operand");
121121
;
@@ -131,7 +131,7 @@ void XtensaInstPrinter::printCallOperand(const MCInst *MI, int OpNum,
131131
OS << '+';
132132
OS << Val;
133133
} else if (MC.isExpr())
134-
MC.getExpr()->print(OS, &MAI, true);
134+
MC.getExpr()->print(OS, &MAI);
135135
else
136136
llvm_unreachable("Invalid operand");
137137
}
@@ -149,7 +149,7 @@ void XtensaInstPrinter::printL32RTarget(const MCInst *MI, int OpNum,
149149
O << ". ";
150150
O << Value;
151151
} else if (MC.isExpr())
152-
MC.getExpr()->print(O, &MAI, true);
152+
MC.getExpr()->print(O, &MAI);
153153
else
154154
llvm_unreachable("Invalid operand");
155155
}

‎llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -35,8 +35,8 @@ declare void @no_op() nounwind;
3535
; CHECK-NEXT: adrp x11, no_op
3636
; CHECK-NEXT: add x11, x11, :lo12:no_op
3737
; CHECK-NEXT: ldr x8, [x8, :lo12:__os_arm64x_check_icall]
38-
; CHECK-NEXT: adrp x10, ($iexit_thunk$cdecl$v$v)
39-
; CHECK-NEXT: add x10, x10, :lo12:($iexit_thunk$cdecl$v$v)
38+
; CHECK-NEXT: adrp x10, $iexit_thunk$cdecl$v$v
39+
; CHECK-NEXT: add x10, x10, :lo12:$iexit_thunk$cdecl$v$v
4040
; CHECK-NEXT: blr x8
4141
; CHECK-NEXT: .seh_startepilogue
4242
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -82,8 +82,8 @@ declare i64 @simple_integers(i8, i16, i32, i64) nounwind;
8282
; CHECK-NEXT: adrp x11, simple_integers
8383
; CHECK-NEXT: add x11, x11, :lo12:simple_integers
8484
; CHECK-NEXT: ldr x8, [x8, :lo12:__os_arm64x_check_icall]
85-
; CHECK-NEXT: adrp x10, ($iexit_thunk$cdecl$i8$i8i8i8i8)
86-
; CHECK-NEXT: add x10, x10, :lo12:($iexit_thunk$cdecl$i8$i8i8i8i8)
85+
; CHECK-NEXT: adrp x10, $iexit_thunk$cdecl$i8$i8i8i8i8
86+
; CHECK-NEXT: add x10, x10, :lo12:$iexit_thunk$cdecl$i8$i8i8i8i8
8787
; CHECK-NEXT: blr x8
8888
; CHECK-NEXT: .seh_startepilogue
8989
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -129,8 +129,8 @@ declare double @simple_floats(float, double) nounwind;
129129
; CHECK-NEXT: adrp x11, simple_floats
130130
; CHECK-NEXT: add x11, x11, :lo12:simple_floats
131131
; CHECK-NEXT: ldr x8, [x8, :lo12:__os_arm64x_check_icall]
132-
; CHECK-NEXT: adrp x10, ($iexit_thunk$cdecl$d$fd)
133-
; CHECK-NEXT: add x10, x10, :lo12:($iexit_thunk$cdecl$d$fd)
132+
; CHECK-NEXT: adrp x10, $iexit_thunk$cdecl$d$fd
133+
; CHECK-NEXT: add x10, x10, :lo12:$iexit_thunk$cdecl$d$fd
134134
; CHECK-NEXT: blr x8
135135
; CHECK-NEXT: .seh_startepilogue
136136
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -176,8 +176,8 @@ declare void @has_varargs(...) nounwind;
176176
; CHECK-NEXT: adrp x11, has_varargs
177177
; CHECK-NEXT: add x11, x11, :lo12:has_varargs
178178
; CHECK-NEXT: ldr x8, [x8, :lo12:__os_arm64x_check_icall]
179-
; CHECK-NEXT: adrp x10, ($iexit_thunk$cdecl$v$varargs)
180-
; CHECK-NEXT: add x10, x10, :lo12:($iexit_thunk$cdecl$v$varargs)
179+
; CHECK-NEXT: adrp x10, $iexit_thunk$cdecl$v$varargs
180+
; CHECK-NEXT: add x10, x10, :lo12:$iexit_thunk$cdecl$v$varargs
181181
; CHECK-NEXT: blr x8
182182
; CHECK-NEXT: .seh_startepilogue
183183
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -223,8 +223,8 @@ declare void @has_sret(ptr sret([100 x i8])) nounwind;
223223
; CHECK-NEXT: adrp x11, has_sret
224224
; CHECK-NEXT: add x11, x11, :lo12:has_sret
225225
; CHECK-NEXT: ldr x9, [x9, :lo12:__os_arm64x_check_icall]
226-
; CHECK-NEXT: adrp x10, ($iexit_thunk$cdecl$m100$v)
227-
; CHECK-NEXT: add x10, x10, :lo12:($iexit_thunk$cdecl$m100$v)
226+
; CHECK-NEXT: adrp x10, $iexit_thunk$cdecl$m100$v
227+
; CHECK-NEXT: add x10, x10, :lo12:$iexit_thunk$cdecl$m100$v
228228
; CHECK-NEXT: blr x9
229229
; CHECK-NEXT: .seh_startepilogue
230230
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -271,8 +271,8 @@ declare void @has_aligned_sret(ptr align 32 sret(%TSRet)) nounwind;
271271
; CHECK: adrp x11, has_aligned_sret
272272
; CHECK: add x11, x11, :lo12:has_aligned_sret
273273
; CHECK: ldr x9, [x9, :lo12:__os_arm64x_check_icall]
274-
; CHECK: adrp x10, ($iexit_thunk$cdecl$m16$v)
275-
; CHECK: add x10, x10, :lo12:($iexit_thunk$cdecl$m16$v)
274+
; CHECK: adrp x10, $iexit_thunk$cdecl$m16$v
275+
; CHECK: add x10, x10, :lo12:$iexit_thunk$cdecl$m16$v
276276
; CHECK: blr x9
277277
; CHECK: .seh_startepilogue
278278
; CHECK: ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -325,8 +325,8 @@ declare [2 x i8] @small_array([2 x i8], [2 x float]) nounwind;
325325
; CHECK-NEXT: adrp x11, small_array
326326
; CHECK-NEXT: add x11, x11, :lo12:small_array
327327
; CHECK-NEXT: ldr x8, [x8, :lo12:__os_arm64x_check_icall]
328-
; CHECK-NEXT: adrp x10, ($iexit_thunk$cdecl$m2$m2F8)
329-
; CHECK-NEXT: add x10, x10, :lo12:($iexit_thunk$cdecl$m2$m2F8)
328+
; CHECK-NEXT: adrp x10, $iexit_thunk$cdecl$m2$m2F8
329+
; CHECK-NEXT: add x10, x10, :lo12:$iexit_thunk$cdecl$m2$m2F8
330330
; CHECK-NEXT: blr x8
331331
; CHECK-NEXT: .seh_startepilogue
332332
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -382,8 +382,8 @@ declare [3 x i64] @large_array([3 x i64], [2 x double], [2 x [2 x i64]]) nounwin
382382
; CHECK-NEXT: adrp x11, large_array
383383
; CHECK-NEXT: add x11, x11, :lo12:large_array
384384
; CHECK-NEXT: ldr x8, [x8, :lo12:__os_arm64x_check_icall]
385-
; CHECK-NEXT: adrp x10, ($iexit_thunk$cdecl$m24$m24D16m32)
386-
; CHECK-NEXT: add x10, x10, :lo12:($iexit_thunk$cdecl$m24$m24D16m32)
385+
; CHECK-NEXT: adrp x10, $iexit_thunk$cdecl$m24$m24D16m32
386+
; CHECK-NEXT: add x10, x10, :lo12:$iexit_thunk$cdecl$m24$m24D16m32
387387
; CHECK-NEXT: blr x8
388388
; CHECK-NEXT: .seh_startepilogue
389389
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -446,8 +446,8 @@ declare %T2 @simple_struct(%T1, %T2, %T3, %T4) nounwind;
446446
; CHECK-NEXT: adrp x11, simple_struct
447447
; CHECK-NEXT: add x11, x11, :lo12:simple_struct
448448
; CHECK-NEXT: ldr x8, [x8, :lo12:__os_arm64x_check_icall]
449-
; CHECK-NEXT: adrp x10, ($iexit_thunk$cdecl$m8$i8m8m16m24)
450-
; CHECK-NEXT: add x10, x10, :lo12:($iexit_thunk$cdecl$m8$i8m8m16m24)
449+
; CHECK-NEXT: adrp x10, $iexit_thunk$cdecl$m8$i8m8m16m24
450+
; CHECK-NEXT: add x10, x10, :lo12:$iexit_thunk$cdecl$m8$i8m8m16m24
451451
; CHECK-NEXT: blr x8
452452
; CHECK-NEXT: .seh_startepilogue
453453
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -499,8 +499,8 @@ declare <4 x i8> @small_vector(<4 x i8> %0) nounwind;
499499
; CHECK-NEXT: adrp x11, small_vector
500500
; CHECK-NEXT: add x11, x11, :lo12:small_vector
501501
; CHECK-NEXT: ldr x8, [x8, :lo12:__os_arm64x_check_icall]
502-
; CHECK-NEXT: adrp x10, ($iexit_thunk$cdecl$m$m)
503-
; CHECK-NEXT: add x10, x10, :lo12:($iexit_thunk$cdecl$m$m)
502+
; CHECK-NEXT: adrp x10, $iexit_thunk$cdecl$m$m
503+
; CHECK-NEXT: add x10, x10, :lo12:$iexit_thunk$cdecl$m$m
504504
; CHECK-NEXT: blr x8
505505
; CHECK-NEXT: .seh_startepilogue
506506
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
@@ -549,8 +549,8 @@ declare <8 x i16> @large_vector(<8 x i16> %0) nounwind;
549549
; CHECK-NEXT: adrp x11, large_vector
550550
; CHECK-NEXT: add x11, x11, :lo12:large_vector
551551
; CHECK-NEXT: ldr x8, [x8, :lo12:__os_arm64x_check_icall]
552-
; CHECK-NEXT: adrp x10, ($iexit_thunk$cdecl$m16$m16)
553-
; CHECK-NEXT: add x10, x10, :lo12:($iexit_thunk$cdecl$m16$m16)
552+
; CHECK-NEXT: adrp x10, $iexit_thunk$cdecl$m16$m16
553+
; CHECK-NEXT: add x10, x10, :lo12:$iexit_thunk$cdecl$m16$m16
554554
; CHECK-NEXT: blr x8
555555
; CHECK-NEXT: .seh_startepilogue
556556
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload

‎llvm/test/CodeGen/AArch64/arm64ec-hybrid-patchable.ll‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -81,8 +81,8 @@ define dso_local void @caller() nounwind {
8181
; CHECK-NEXT: adrp x11, func
8282
; CHECK-NEXT: add x11, x11, :lo12:func
8383
; CHECK-NEXT: ldr x8, [x8, :lo12:__os_arm64x_check_icall]
84-
; CHECK-NEXT: adrp x10, ($iexit_thunk$cdecl$v$v)
85-
; CHECK-NEXT: add x10, x10, :lo12:($iexit_thunk$cdecl$v$v)
84+
; CHECK-NEXT: adrp x10, $iexit_thunk$cdecl$v$v
85+
; CHECK-NEXT: add x10, x10, :lo12:$iexit_thunk$cdecl$v$v
8686
; CHECK-NEXT: str x11, [sp, #8]
8787
; CHECK-NEXT: blr x8
8888
; CHECK-NEXT: blr x11
@@ -111,8 +111,8 @@ define dso_local void @caller() nounwind {
111111
; CHECK-NEXT: adrp x11, func
112112
; CHECK-NEXT: add x11, x11, :lo12:func
113113
; CHECK-NEXT: ldr x8, [x8, :lo12:__os_arm64x_dispatch_call]
114-
; CHECK-NEXT: adrp x10, ($iexit_thunk$cdecl$i8$v)
115-
; CHECK-NEXT: add x10, x10, :lo12:($iexit_thunk$cdecl$i8$v)
114+
; CHECK-NEXT: adrp x10, $iexit_thunk$cdecl$i8$v
115+
; CHECK-NEXT: add x10, x10, :lo12:$iexit_thunk$cdecl$i8$v
116116
; CHECK-NEXT: adrp x9, "#func$hp_target"
117117
; CHECK-NEXT: add x9, x9, :lo12:"#func$hp_target"
118118
; CHECK-NEXT: blr x8
@@ -138,8 +138,8 @@ define dso_local void @caller() nounwind {
138138
; CHECK-NEXT: adrp x11, has_varargs
139139
; CHECK-NEXT: add x11, x11, :lo12:has_varargs
140140
; CHECK-NEXT: ldr x8, [x8, :lo12:__os_arm64x_dispatch_call]
141-
; CHECK-NEXT: adrp x10, ($iexit_thunk$cdecl$v$varargs)
142-
; CHECK-NEXT: add x10, x10, :lo12:($iexit_thunk$cdecl$v$varargs)
141+
; CHECK-NEXT: adrp x10, $iexit_thunk$cdecl$v$varargs
142+
; CHECK-NEXT: add x10, x10, :lo12:$iexit_thunk$cdecl$v$varargs
143143
; CHECK-NEXT: adrp x9, "#has_varargs$hp_target"
144144
; CHECK-NEXT: add x9, x9, :lo12:"#has_varargs$hp_target"
145145
; CHECK-NEXT: blr x8
@@ -165,8 +165,8 @@ define dso_local void @caller() nounwind {
165165
; CHECK-NEXT: adrp x11, has_sret
166166
; CHECK-NEXT: add x11, x11, :lo12:has_sret
167167
; CHECK-NEXT: ldr x12, [x9, :lo12:__os_arm64x_dispatch_call]
168-
; CHECK-NEXT: adrp x10, ($iexit_thunk$cdecl$m100$v)
169-
; CHECK-NEXT: add x10, x10, :lo12:($iexit_thunk$cdecl$m100$v)
168+
; CHECK-NEXT: adrp x10, $iexit_thunk$cdecl$m100$v
169+
; CHECK-NEXT: add x10, x10, :lo12:$iexit_thunk$cdecl$m100$v
170170
; CHECK-NEXT: adrp x9, "#has_sret$hp_target"
171171
; CHECK-NEXT: add x9, x9, :lo12:"#has_sret$hp_target"
172172
; CHECK-NEXT: blr x12
@@ -192,8 +192,8 @@ define dso_local void @caller() nounwind {
192192
; CHECK-NEXT: adrp x11, exp
193193
; CHECK-NEXT: add x11, x11, :lo12:exp
194194
; CHECK-NEXT: ldr x8, [x8, :lo12:__os_arm64x_dispatch_call]
195-
; CHECK-NEXT: adrp x10, ($iexit_thunk$cdecl$v$v)
196-
; CHECK-NEXT: add x10, x10, :lo12:($iexit_thunk$cdecl$v$v)
195+
; CHECK-NEXT: adrp x10, $iexit_thunk$cdecl$v$v
196+
; CHECK-NEXT: add x10, x10, :lo12:$iexit_thunk$cdecl$v$v
197197
; CHECK-NEXT: adrp x9, "#exp$hp_target"
198198
; CHECK-NEXT: add x9, x9, :lo12:"#exp$hp_target"
199199
; CHECK-NEXT: blr x8

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