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[ELF] Pass Ctx & to Mips
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+49
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‎lld/ELF/Arch/Mips.cpp‎

Lines changed: 49 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -211,7 +211,8 @@ void MIPS<ELFT>::writeGotPlt(uint8_t *buf, const Symbol &) const {
211211
write32(ctx, buf, va);
212212
}
213213

214-
template <endianness E> static uint32_t readShuffle(const uint8_t *loc) {
214+
template <endianness E>
215+
static uint32_t readShuffle(Ctx &ctx, const uint8_t *loc) {
215216
// The major opcode of a microMIPS instruction needs to appear
216217
// in the first 16-bit word (lowest address) for efficient hardware
217218
// decode so that it knows if the instruction is 16-bit or 32-bit
@@ -224,7 +225,7 @@ template <endianness E> static uint32_t readShuffle(const uint8_t *loc) {
224225
return v;
225226
}
226227

227-
static void writeValue(uint8_t *loc, uint64_t v, uint8_t bitsSize,
228+
static void writeValue(Ctx &ctx, uint8_t *loc, uint64_t v, uint8_t bitsSize,
228229
uint8_t shift) {
229230
uint32_t instr = read32(ctx, loc);
230231
uint32_t mask = 0xffffffff >> (32 - bitsSize);
@@ -233,14 +234,14 @@ static void writeValue(uint8_t *loc, uint64_t v, uint8_t bitsSize,
233234
}
234235

235236
template <endianness E>
236-
static void writeShuffleValue(uint8_t *loc, uint64_t v, uint8_t bitsSize,
237-
uint8_t shift) {
237+
static void writeShuffle(Ctx &ctx, uint8_t *loc, uint64_t v, uint8_t bitsSize,
238+
uint8_t shift) {
238239
// See comments in readShuffle for purpose of this code.
239240
uint16_t *words = (uint16_t *)loc;
240241
if (E == llvm::endianness::little)
241242
std::swap(words[0], words[1]);
242243

243-
writeValue(loc, v, bitsSize, shift);
244+
writeValue(ctx, loc, v, bitsSize, shift);
244245

245246
if (E == llvm::endianness::little)
246247
std::swap(words[0], words[1]);
@@ -312,9 +313,9 @@ template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *buf) const {
312313
write32(ctx, buf + 28, 0x2718fffe); // subu $24, $24, 2
313314

314315
uint64_t gotPlt = ctx.in.gotPlt->getVA();
315-
writeValue(buf, gotPlt + 0x8000, 16, 16);
316-
writeValue(buf + 4, gotPlt, 16, 0);
317-
writeValue(buf + 8, gotPlt, 16, 0);
316+
writeValue(ctx, buf, gotPlt + 0x8000, 16, 16);
317+
writeValue(ctx, buf + 4, gotPlt, 16, 0);
318+
writeValue(ctx, buf + 8, gotPlt, 16, 0);
318319
}
319320

320321
template <class ELFT>
@@ -351,9 +352,9 @@ void MIPS<ELFT>::writePlt(uint8_t *buf, const Symbol &sym,
351352
write32(ctx, buf + 4, loadInst); // l[wd] $25, %lo(.got.plt entry)($15)
352353
write32(ctx, buf + 8, jrInst); // jr $25 / jr.hb $25
353354
write32(ctx, buf + 12, addInst); // [d]addiu $24, $15, %lo(.got.plt entry)
354-
writeValue(buf, gotPltEntryAddr + 0x8000, 16, 16);
355-
writeValue(buf + 4, gotPltEntryAddr, 16, 0);
356-
writeValue(buf + 12, gotPltEntryAddr, 16, 0);
355+
writeValue(ctx, buf, gotPltEntryAddr + 0x8000, 16, 16);
356+
writeValue(ctx, buf + 4, gotPltEntryAddr, 16, 0);
357+
writeValue(ctx, buf + 12, gotPltEntryAddr, 16, 0);
357358
}
358359

359360
template <class ELFT>
@@ -418,7 +419,7 @@ int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *buf, RelType type) const {
418419
return SignExtend64<16>(read32(ctx, buf));
419420
case R_MICROMIPS_GOT16:
420421
case R_MICROMIPS_HI16:
421-
return SignExtend64<16>(readShuffle<e>(buf)) << 16;
422+
return SignExtend64<16>(readShuffle<e>(ctx, buf)) << 16;
422423
case R_MICROMIPS_CALL16:
423424
case R_MICROMIPS_GPREL16:
424425
case R_MICROMIPS_LO16:
@@ -429,9 +430,9 @@ int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *buf, RelType type) const {
429430
case R_MICROMIPS_TLS_LDM:
430431
case R_MICROMIPS_TLS_TPREL_HI16:
431432
case R_MICROMIPS_TLS_TPREL_LO16:
432-
return SignExtend64<16>(readShuffle<e>(buf));
433+
return SignExtend64<16>(readShuffle<e>(ctx, buf));
433434
case R_MICROMIPS_GPREL7_S2:
434-
return SignExtend64<9>(readShuffle<e>(buf) << 2);
435+
return SignExtend64<9>(readShuffle<e>(ctx, buf) << 2);
435436
case R_MIPS_PC16:
436437
return SignExtend64<18>(read32(ctx, buf) << 2);
437438
case R_MIPS_PC19_S2:
@@ -443,23 +444,23 @@ int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *buf, RelType type) const {
443444
case R_MIPS_PC32:
444445
return SignExtend64<32>(read32(ctx, buf));
445446
case R_MICROMIPS_26_S1:
446-
return SignExtend64<27>(readShuffle<e>(buf) << 1);
447+
return SignExtend64<27>(readShuffle<e>(ctx, buf) << 1);
447448
case R_MICROMIPS_PC7_S1:
448449
return SignExtend64<8>(read16(ctx, buf) << 1);
449450
case R_MICROMIPS_PC10_S1:
450451
return SignExtend64<11>(read16(ctx, buf) << 1);
451452
case R_MICROMIPS_PC16_S1:
452-
return SignExtend64<17>(readShuffle<e>(buf) << 1);
453+
return SignExtend64<17>(readShuffle<e>(ctx, buf) << 1);
453454
case R_MICROMIPS_PC18_S3:
454-
return SignExtend64<21>(readShuffle<e>(buf) << 3);
455+
return SignExtend64<21>(readShuffle<e>(ctx, buf) << 3);
455456
case R_MICROMIPS_PC19_S2:
456-
return SignExtend64<21>(readShuffle<e>(buf) << 2);
457+
return SignExtend64<21>(readShuffle<e>(ctx, buf) << 2);
457458
case R_MICROMIPS_PC21_S1:
458-
return SignExtend64<22>(readShuffle<e>(buf) << 1);
459+
return SignExtend64<22>(readShuffle<e>(ctx, buf) << 1);
459460
case R_MICROMIPS_PC23_S2:
460-
return SignExtend64<25>(readShuffle<e>(buf) << 2);
461+
return SignExtend64<25>(readShuffle<e>(ctx, buf) << 2);
461462
case R_MICROMIPS_PC26_S1:
462-
return SignExtend64<27>(readShuffle<e>(buf) << 1);
463+
return SignExtend64<27>(readShuffle<e>(ctx, buf) << 1);
463464
case R_MIPS_64:
464465
case R_MIPS_TLS_DTPMOD64:
465466
case R_MIPS_TLS_DTPREL64:
@@ -534,16 +535,16 @@ static uint64_t fixupCrossModeJump(uint8_t *loc, RelType type, uint64_t val) {
534535
case R_MIPS_26: {
535536
uint32_t inst = read32(ctx, loc) >> 26;
536537
if (inst == 0x3 || inst == 0x1d) { // JAL or JALX
537-
writeValue(loc, 0x1d << 26, 32, 0);
538+
writeValue(ctx, loc, 0x1d << 26, 32, 0);
538539
return val;
539540
}
540541
break;
541542
}
542543
case R_MICROMIPS_26_S1: {
543-
uint32_t inst = readShuffle<e>(loc) >> 26;
544+
uint32_t inst = readShuffle<e>(ctx, loc) >> 26;
544545
if (inst == 0x3d || inst == 0x3c) { // JAL32 or JALX32
545546
val >>= 1;
546-
writeShuffleValue<e>(loc, 0x3c << 26, 32, 0);
547+
writeShuffle<e>(ctx, loc, 0x3c << 26, 32, 0);
547548
return val;
548549
}
549550
break;
@@ -600,25 +601,25 @@ void MIPS<ELFT>::relocate(uint8_t *loc, const Relocation &rel,
600601
write64(ctx, loc, val);
601602
break;
602603
case R_MIPS_26:
603-
writeValue(loc, val, 26, 2);
604+
writeValue(ctx, loc, val, 26, 2);
604605
break;
605606
case R_MIPS_GOT16:
606607
// The R_MIPS_GOT16 relocation's value in "relocatable" linking mode
607608
// is updated addend (not a GOT index). In that case write high 16 bits
608609
// to store a correct addend value.
609610
if (ctx.arg.relocatable) {
610-
writeValue(loc, val + 0x8000, 16, 16);
611+
writeValue(ctx, loc, val + 0x8000, 16, 16);
611612
} else {
612613
checkInt(loc, val, 16, rel);
613-
writeValue(loc, val, 16, 0);
614+
writeValue(ctx, loc, val, 16, 0);
614615
}
615616
break;
616617
case R_MICROMIPS_GOT16:
617618
if (ctx.arg.relocatable) {
618-
writeShuffleValue<e>(loc, val + 0x8000, 16, 16);
619+
writeShuffle<e>(ctx, loc, val + 0x8000, 16, 16);
619620
} else {
620621
checkInt(loc, val, 16, rel);
621-
writeShuffleValue<e>(loc, val, 16, 0);
622+
writeShuffle<e>(ctx, loc, val, 16, 0);
622623
}
623624
break;
624625
case R_MIPS_CALL16:
@@ -637,46 +638,46 @@ void MIPS<ELFT>::relocate(uint8_t *loc, const Relocation &rel,
637638
case R_MIPS_PCLO16:
638639
case R_MIPS_TLS_DTPREL_LO16:
639640
case R_MIPS_TLS_TPREL_LO16:
640-
writeValue(loc, val, 16, 0);
641+
writeValue(ctx, loc, val, 16, 0);
641642
break;
642643
case R_MICROMIPS_GPREL16:
643644
case R_MICROMIPS_TLS_GD:
644645
case R_MICROMIPS_TLS_LDM:
645646
checkInt(loc, val, 16, rel);
646-
writeShuffleValue<e>(loc, val, 16, 0);
647+
writeShuffle<e>(ctx, loc, val, 16, 0);
647648
break;
648649
case R_MICROMIPS_CALL16:
649650
case R_MICROMIPS_CALL_LO16:
650651
case R_MICROMIPS_LO16:
651652
case R_MICROMIPS_TLS_DTPREL_LO16:
652653
case R_MICROMIPS_TLS_GOTTPREL:
653654
case R_MICROMIPS_TLS_TPREL_LO16:
654-
writeShuffleValue<e>(loc, val, 16, 0);
655+
writeShuffle<e>(ctx, loc, val, 16, 0);
655656
break;
656657
case R_MICROMIPS_GPREL7_S2:
657658
checkInt(loc, val, 7, rel);
658-
writeShuffleValue<e>(loc, val, 7, 2);
659+
writeShuffle<e>(ctx, loc, val, 7, 2);
659660
break;
660661
case R_MIPS_CALL_HI16:
661662
case R_MIPS_GOT_HI16:
662663
case R_MIPS_HI16:
663664
case R_MIPS_PCHI16:
664665
case R_MIPS_TLS_DTPREL_HI16:
665666
case R_MIPS_TLS_TPREL_HI16:
666-
writeValue(loc, val + 0x8000, 16, 16);
667+
writeValue(ctx, loc, val + 0x8000, 16, 16);
667668
break;
668669
case R_MICROMIPS_CALL_HI16:
669670
case R_MICROMIPS_GOT_HI16:
670671
case R_MICROMIPS_HI16:
671672
case R_MICROMIPS_TLS_DTPREL_HI16:
672673
case R_MICROMIPS_TLS_TPREL_HI16:
673-
writeShuffleValue<e>(loc, val + 0x8000, 16, 16);
674+
writeShuffle<e>(ctx, loc, val + 0x8000, 16, 16);
674675
break;
675676
case R_MIPS_HIGHER:
676-
writeValue(loc, val + 0x80008000, 16, 32);
677+
writeValue(ctx, loc, val + 0x80008000, 16, 32);
677678
break;
678679
case R_MIPS_HIGHEST:
679-
writeValue(loc, val + 0x800080008000, 16, 48);
680+
writeValue(ctx, loc, val + 0x800080008000, 16, 48);
680681
break;
681682
case R_MIPS_JALR:
682683
val -= 4;
@@ -699,30 +700,30 @@ void MIPS<ELFT>::relocate(uint8_t *loc, const Relocation &rel,
699700
case R_MIPS_PC16:
700701
checkAlignment(loc, val, 4, rel);
701702
checkInt(loc, val, 18, rel);
702-
writeValue(loc, val, 16, 2);
703+
writeValue(ctx, loc, val, 16, 2);
703704
break;
704705
case R_MIPS_PC19_S2:
705706
checkAlignment(loc, val, 4, rel);
706707
checkInt(loc, val, 21, rel);
707-
writeValue(loc, val, 19, 2);
708+
writeValue(ctx, loc, val, 19, 2);
708709
break;
709710
case R_MIPS_PC21_S2:
710711
checkAlignment(loc, val, 4, rel);
711712
checkInt(loc, val, 23, rel);
712-
writeValue(loc, val, 21, 2);
713+
writeValue(ctx, loc, val, 21, 2);
713714
break;
714715
case R_MIPS_PC26_S2:
715716
checkAlignment(loc, val, 4, rel);
716717
checkInt(loc, val, 28, rel);
717-
writeValue(loc, val, 26, 2);
718+
writeValue(ctx, loc, val, 26, 2);
718719
break;
719720
case R_MIPS_PC32:
720-
writeValue(loc, val, 32, 0);
721+
writeValue(ctx, loc, val, 32, 0);
721722
break;
722723
case R_MICROMIPS_26_S1:
723724
case R_MICROMIPS_PC26_S1:
724725
checkInt(loc, val, 27, rel);
725-
writeShuffleValue<e>(loc, val, 26, 1);
726+
writeShuffle<e>(ctx, loc, val, 26, 1);
726727
break;
727728
case R_MICROMIPS_PC7_S1:
728729
checkInt(loc, val, 8, rel);
@@ -734,23 +735,23 @@ void MIPS<ELFT>::relocate(uint8_t *loc, const Relocation &rel,
734735
break;
735736
case R_MICROMIPS_PC16_S1:
736737
checkInt(loc, val, 17, rel);
737-
writeShuffleValue<e>(loc, val, 16, 1);
738+
writeShuffle<e>(ctx, loc, val, 16, 1);
738739
break;
739740
case R_MICROMIPS_PC18_S3:
740741
checkInt(loc, val, 21, rel);
741-
writeShuffleValue<e>(loc, val, 18, 3);
742+
writeShuffle<e>(ctx, loc, val, 18, 3);
742743
break;
743744
case R_MICROMIPS_PC19_S2:
744745
checkInt(loc, val, 21, rel);
745-
writeShuffleValue<e>(loc, val, 19, 2);
746+
writeShuffle<e>(ctx, loc, val, 19, 2);
746747
break;
747748
case R_MICROMIPS_PC21_S1:
748749
checkInt(loc, val, 22, rel);
749-
writeShuffleValue<e>(loc, val, 21, 1);
750+
writeShuffle<e>(ctx, loc, val, 21, 1);
750751
break;
751752
case R_MICROMIPS_PC23_S2:
752753
checkInt(loc, val, 25, rel);
753-
writeShuffleValue<e>(loc, val, 23, 2);
754+
writeShuffle<e>(ctx, loc, val, 23, 2);
754755
break;
755756
default:
756757
llvm_unreachable("unknown relocation");

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