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[RISCV][GISel] Make loads/stores with s16 register type and s16 memory type legal.
This is needed to support Zfh loads/stores. This requires supporting extends from sext/zext form i16 and s16 G_FREEZE to support the current tests we have.
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10 files changed

+112
-39
lines changed

10 files changed

+112
-39
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp‎

Lines changed: 17 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -154,9 +154,10 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
154154
.clampScalar(0, sXLen, sXLen);
155155

156156
getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
157+
.legalFor({{sXLen, s16}})
158+
.legalFor(ST.is64Bit(), {{s64, s32}})
157159
.legalIf(all(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST),
158160
typeIsLegalIntOrFPVec(1, IntOrFPVecTys, ST)))
159-
.legalFor(ST.is64Bit(), {{sXLen, s32}})
160161
.customIf(typeIsLegalBoolVec(1, BoolVecTys, ST))
161162
.maxScalar(0, sXLen);
162163

@@ -234,8 +235,18 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
234235
.clampScalar(0, sXLen, sXLen);
235236

236237
// TODO: transform illegal vector types into legal vector type
238+
getActionDefinitionsBuilder(G_FREEZE)
239+
.legalFor({s16, s32, p0})
240+
.legalFor(ST.is64Bit(), {s64})
241+
.legalIf(typeIsLegalBoolVec(0, BoolVecTys, ST))
242+
.legalIf(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST))
243+
.widenScalarToNextPow2(0)
244+
.clampScalar(0, s16, sXLen);
245+
246+
// TODO: transform illegal vector types into legal vector type
247+
// TODO: Merge with G_FREEZE?
237248
getActionDefinitionsBuilder(
238-
{G_IMPLICIT_DEF, G_CONSTANT_FOLD_BARRIER, G_FREEZE})
249+
{G_IMPLICIT_DEF, G_CONSTANT_FOLD_BARRIER})
239250
.legalFor({s32, sXLen, p0})
240251
.legalIf(typeIsLegalBoolVec(0, BoolVecTys, ST))
241252
.legalIf(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST))
@@ -271,12 +282,14 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
271282
};
272283

273284
LoadActions.legalForTypesWithMemDesc(
274-
{{s32, p0, s8, getScalarMemAlign(8)},
285+
{{s16, p0, s16, getScalarMemAlign(16)},
286+
{s32, p0, s8, getScalarMemAlign(8)},
275287
{s32, p0, s16, getScalarMemAlign(16)},
276288
{s32, p0, s32, getScalarMemAlign(32)},
277289
{p0, p0, sXLen, getScalarMemAlign(XLen)}});
278290
StoreActions.legalForTypesWithMemDesc(
279-
{{s32, p0, s8, getScalarMemAlign(8)},
291+
{{s16, p0, s16, getScalarMemAlign(16)},
292+
{s32, p0, s8, getScalarMemAlign(8)},
280293
{s32, p0, s16, getScalarMemAlign(16)},
281294
{s32, p0, s32, getScalarMemAlign(32)},
282295
{p0, p0, sXLen, getScalarMemAlign(XLen)}});

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -523,6 +523,8 @@ def FeatureStdExtZbkb
523523
def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
524524
AssemblerPredicate<(all_of FeatureStdExtZbkb),
525525
"'Zbkb' (Bitmanip instructions for Cryptography)">;
526+
def NoStdExtZbkb : Predicate<"!Subtarget->hasStdExtZbkb()">,
527+
AssemblerPredicate<(all_of (not FeatureStdExtZbkb))>;
526528

527529
def FeatureStdExtZbkx
528530
: RISCVExtension<"zbkx", 1, 0,

‎llvm/lib/Target/RISCV/RISCVGISel.td‎

Lines changed: 31 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -200,14 +200,42 @@ def : Pat<(i32 (trunc GPR:$src)), (COPY GPR:$src)>;
200200
def : Pat<(zext_is_sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;
201201
}
202202

203-
let Predicates = [IsRV64, NotHasStdExtZba] in {
203+
let Predicates = [IsRV64, NotHasStdExtZba] in
204204
def : Pat<(zext (i32 GPR:$src)), (SRLI (i64 (SLLI GPR:$src, 32)), 32)>;
205-
}
205+
206+
let Predicates = [IsRV32, NoStdExtZbb, NoStdExtZbkb] in
207+
def : Pat<(XLenVT (zext (i16 GPR:$src))),
208+
(SRLI (XLenVT (SLLI GPR:$src, 16)), 16)>;
209+
210+
let Predicates = [IsRV64, NoStdExtZbb, NoStdExtZbkb] in
211+
def : Pat<(i64 (zext (i16 GPR:$src))),
212+
(SRLI (XLenVT (SLLI GPR:$src, 48)), 48)>;
213+
214+
let Predicates = [IsRV32, NoStdExtZbb] in
215+
def : Pat<(XLenVT (sext (i16 GPR:$src))),
216+
(SRAI (XLenVT (SLLI GPR:$src, 16)), 16)>;
217+
218+
let Predicates = [IsRV64, NoStdExtZbb] in
219+
def : Pat<(i64 (sext (i16 GPR:$src))),
220+
(SRAI (XLenVT (SLLI GPR:$src, 48)), 48)>;
206221

207222
//===----------------------------------------------------------------------===//
208-
// Zb* RV64 i32 patterns not used by SelectionDAG.
223+
// Zb* RV64 patterns not used by SelectionDAG.
209224
//===----------------------------------------------------------------------===//
210225

211226
let Predicates = [HasStdExtZba, IsRV64] in {
212227
def : Pat<(zext (i32 GPR:$src)), (ADD_UW GPR:$src, (XLenVT X0))>;
213228
}
229+
230+
let Predicates= [HasStdExtZbb] in
231+
def : Pat<(XLenVT (sext (i16 GPR:$rs))), (SEXT_H GPR:$rs)>;
232+
233+
let Predicates = [HasStdExtZbb, IsRV32] in
234+
def : Pat<(i32 (zext (i16 GPR:$rs))), (ZEXT_H_RV32 GPR:$rs)>;
235+
let Predicates = [HasStdExtZbb, IsRV64] in
236+
def : Pat<(i64 (zext (i16 GPR:$rs))), (ZEXT_H_RV64 GPR:$rs)>;
237+
238+
let Predicates = [HasStdExtZbkb, NoStdExtZbb, IsRV32] in
239+
def : Pat<(i32 (zext (i16 GPR:$rs))), (PACK GPR:$rs, (XLenVT X0))>;
240+
let Predicates = [HasStdExtZbkb, NoStdExtZbb, IsRV64] in
241+
def : Pat<(i64 (zext (i16 GPR:$rs))), (PACKW GPR:$rs, (XLenVT X0))>;

‎llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll‎

Lines changed: 33 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2-
; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+zfh,+m,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV32
3-
; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+zfh,+m,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV64
2+
; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+zfh,+m,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3+
; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+zfh,+m,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
44

55
define i32 @freeze_int(i32 %x) {
66
; CHECK-LABEL: freeze_int:
@@ -130,19 +130,17 @@ define i32 @freeze_anonstruct2(ptr %p) {
130130
; RV32: # %bb.0:
131131
; RV32-NEXT: lh a1, 4(a0)
132132
; RV32-NEXT: lw a0, 0(a0)
133-
; RV32-NEXT: lui a2, 16
134-
; RV32-NEXT: addi a2, a2, -1
135-
; RV32-NEXT: and a1, a1, a2
133+
; RV32-NEXT: slli a1, a1, 16
134+
; RV32-NEXT: srli a1, a1, 16
136135
; RV32-NEXT: add a0, a0, a1
137136
; RV32-NEXT: ret
138137
;
139138
; RV64-LABEL: freeze_anonstruct2:
140139
; RV64: # %bb.0:
141140
; RV64-NEXT: lh a1, 4(a0)
142141
; RV64-NEXT: lw a0, 0(a0)
143-
; RV64-NEXT: lui a2, 16
144-
; RV64-NEXT: addiw a2, a2, -1
145-
; RV64-NEXT: and a1, a1, a2
142+
; RV64-NEXT: slli a1, a1, 48
143+
; RV64-NEXT: srli a1, a1, 48
146144
; RV64-NEXT: add a0, a0, a1
147145
; RV64-NEXT: ret
148146
%s = load {i32, i16}, ptr %p
@@ -154,6 +152,33 @@ define i32 @freeze_anonstruct2(ptr %p) {
154152
ret i32 %t1
155153
}
156154

155+
define i32 @freeze_anonstruct2_sext(ptr %p) {
156+
; RV32-LABEL: freeze_anonstruct2_sext:
157+
; RV32: # %bb.0:
158+
; RV32-NEXT: lh a1, 4(a0)
159+
; RV32-NEXT: lw a0, 0(a0)
160+
; RV32-NEXT: slli a1, a1, 16
161+
; RV32-NEXT: srai a1, a1, 16
162+
; RV32-NEXT: add a0, a0, a1
163+
; RV32-NEXT: ret
164+
;
165+
; RV64-LABEL: freeze_anonstruct2_sext:
166+
; RV64: # %bb.0:
167+
; RV64-NEXT: lh a1, 4(a0)
168+
; RV64-NEXT: lw a0, 0(a0)
169+
; RV64-NEXT: slli a1, a1, 48
170+
; RV64-NEXT: srai a1, a1, 48
171+
; RV64-NEXT: add a0, a0, a1
172+
; RV64-NEXT: ret
173+
%s = load {i32, i16}, ptr %p
174+
%y1 = freeze {i32, i16} %s
175+
%v1 = extractvalue {i32, i16} %y1, 0
176+
%v2 = extractvalue {i32, i16} %y1, 1
177+
%z2 = sext i16 %v2 to i32
178+
%t1 = add i32 %v1, %z2
179+
ret i32 %t1
180+
}
181+
157182
define i32 @freeze_array(ptr %p) nounwind {
158183
; CHECK-LABEL: freeze_array:
159184
; CHECK: # %bb.0:

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -run-pass=instruction-select %s -o - \
3-
# RUN: -disable-gisel-legality-check | FileCheck %s
3+
# RUN: | FileCheck %s
44
# RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -run-pass=instruction-select %s -o - \
5-
# RUN: -disable-gisel-legality-check | FileCheck %s
5+
# RUN: | FileCheck %s
66

77
---
88
name: fp_store_f32

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -143,7 +143,6 @@
143143
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
144144
#
145145
# DEBUG-NEXT: G_FREEZE (opcode {{[0-9]+}}): 1 type index, 0 imm indices
146-
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
147146
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
148147
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
149148

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir‎

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -64,16 +64,18 @@ body: |
6464
; CHECK: liveins: $x10
6565
; CHECK-NEXT: {{ $}}
6666
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
67-
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
68-
; CHECK-NEXT: $x10 = COPY [[LOAD]](s32)
67+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16))
68+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s16)
69+
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s32)
6970
; CHECK-NEXT: PseudoRET implicit $x10
7071
;
7172
; UNALIGNED-LABEL: name: load_i16
7273
; UNALIGNED: liveins: $x10
7374
; UNALIGNED-NEXT: {{ $}}
7475
; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
75-
; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
76-
; UNALIGNED-NEXT: $x10 = COPY [[LOAD]](s32)
76+
; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16))
77+
; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s16)
78+
; UNALIGNED-NEXT: $x10 = COPY [[ANYEXT]](s32)
7779
; UNALIGNED-NEXT: PseudoRET implicit $x10
7880
%0:_(p0) = COPY $x10
7981
%1:_(s16) = G_LOAD %0(p0) :: (load (s16))
@@ -240,8 +242,9 @@ body: |
240242
; UNALIGNED: liveins: $x10
241243
; UNALIGNED-NEXT: {{ $}}
242244
; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
243-
; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16), align 1)
244-
; UNALIGNED-NEXT: $x10 = COPY [[LOAD]](s32)
245+
; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16), align 1)
246+
; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s16)
247+
; UNALIGNED-NEXT: $x10 = COPY [[ANYEXT]](s32)
245248
; UNALIGNED-NEXT: PseudoRET implicit $x10
246249
%0:_(p0) = COPY $x10
247250
%1:_(s16) = G_LOAD %0(p0) :: (load (s16), align 1)

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -66,17 +66,17 @@ body: |
6666
; CHECK: liveins: $x10
6767
; CHECK-NEXT: {{ $}}
6868
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
69-
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
70-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
69+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16))
70+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s16)
7171
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
7272
; CHECK-NEXT: PseudoRET implicit $x10
7373
;
7474
; UNALIGNED-LABEL: name: load_i16
7575
; UNALIGNED: liveins: $x10
7676
; UNALIGNED-NEXT: {{ $}}
7777
; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
78-
; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
79-
; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
78+
; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16))
79+
; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s16)
8080
; UNALIGNED-NEXT: $x10 = COPY [[ANYEXT]](s64)
8181
; UNALIGNED-NEXT: PseudoRET implicit $x10
8282
%0:_(p0) = COPY $x10
@@ -286,8 +286,8 @@ body: |
286286
; UNALIGNED: liveins: $x10
287287
; UNALIGNED-NEXT: {{ $}}
288288
; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
289-
; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16), align 1)
290-
; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
289+
; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16), align 1)
290+
; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s16)
291291
; UNALIGNED-NEXT: $x10 = COPY [[ANYEXT]](s64)
292292
; UNALIGNED-NEXT: PseudoRET implicit $x10
293293
%0:_(p0) = COPY $x10

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -64,16 +64,18 @@ body: |
6464
; CHECK: liveins: $x10, $x11
6565
; CHECK-NEXT: {{ $}}
6666
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
67+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
6768
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
68-
; CHECK-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s16))
69+
; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s16))
6970
; CHECK-NEXT: PseudoRET
7071
;
7172
; UNALIGNED-LABEL: name: store_i16
7273
; UNALIGNED: liveins: $x10, $x11
7374
; UNALIGNED-NEXT: {{ $}}
7475
; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
76+
; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
7577
; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
76-
; UNALIGNED-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s16))
78+
; UNALIGNED-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s16))
7779
; UNALIGNED-NEXT: PseudoRET
7880
%2:_(s32) = COPY $x10
7981
%0:_(s16) = G_TRUNC %2(s32)
@@ -241,8 +243,9 @@ body: |
241243
; UNALIGNED: liveins: $x10, $x11
242244
; UNALIGNED-NEXT: {{ $}}
243245
; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
246+
; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
244247
; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
245-
; UNALIGNED-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s16), align 1)
248+
; UNALIGNED-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s16), align 1)
246249
; UNALIGNED-NEXT: PseudoRET
247250
%2:_(s32) = COPY $x10
248251
%0:_(s16) = G_TRUNC %2(s32)

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -66,18 +66,18 @@ body: |
6666
; CHECK: liveins: $x10, $x11
6767
; CHECK-NEXT: {{ $}}
6868
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
69+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
6970
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
70-
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
71-
; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s16))
71+
; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s16))
7272
; CHECK-NEXT: PseudoRET
7373
;
7474
; UNALIGNED-LABEL: name: store_i16
7575
; UNALIGNED: liveins: $x10, $x11
7676
; UNALIGNED-NEXT: {{ $}}
7777
; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
78+
; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
7879
; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
79-
; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
80-
; UNALIGNED-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s16))
80+
; UNALIGNED-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s16))
8181
; UNALIGNED-NEXT: PseudoRET
8282
%2:_(s64) = COPY $x10
8383
%0:_(s16) = G_TRUNC %2(s64)
@@ -276,9 +276,9 @@ body: |
276276
; UNALIGNED: liveins: $x10, $x11
277277
; UNALIGNED-NEXT: {{ $}}
278278
; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
279+
; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
279280
; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
280-
; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
281-
; UNALIGNED-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s16), align 1)
281+
; UNALIGNED-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s16), align 1)
282282
; UNALIGNED-NEXT: PseudoRET
283283
%2:_(s64) = COPY $x10
284284
%0:_(s16) = G_TRUNC %2(s64)

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